[Mesa-dev] [PATCH 07/16] radeonsi: split si_emit_shader_pointer

[Marek Olšák]

From: Marek Olšák <marek.ol...@amd.com>

---
 src/gallium/drivers/radeonsi/si_descriptors.c | 34 ++++++++++++++++++---------
 1 file changed, 23 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 6e1fd80..a0f3dcf 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1947,39 +1947,51 @@ void si_shader_change_notify(struct si_context *sctx)
                        si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
                                              
R_00B330_SPI_SHADER_USER_DATA_ES_0);
                else
                        si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL,
                                              
R_00B130_SPI_SHADER_USER_DATA_VS_0);
        } else {
                si_set_user_data_base(sctx, PIPE_SHADER_TESS_EVAL, 0);
        }
 }
 
-static void si_emit_shader_pointer(struct si_context *sctx,
-                                  struct si_descriptors *desc,
-                                  unsigned sh_base)
+static void si_emit_shader_pointer_head(struct radeon_winsys_cs *cs,
+                                       struct si_descriptors *desc,
+                                       unsigned sh_base,
+                                       unsigned pointer_count)
 {
-       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
-       uint64_t va;
+       radeon_emit(cs, PKT3(PKT3_SET_SH_REG, pointer_count * 2, 0));
+       radeon_emit(cs, (sh_base + desc->shader_userdata_offset - 
SI_SH_REG_OFFSET) >> 2);
+}
 
-       if (!desc->buffer)
-               return; /* the pointer is not used by current shaders */
+static void si_emit_shader_pointer_body(struct radeon_winsys_cs *cs,
+                                       struct si_descriptors *desc)
+{
+       uint64_t va = 0;
 
-       va = desc->buffer->gpu_address +
-            desc->buffer_offset;
+       if (desc->buffer)
+               va = desc->buffer->gpu_address + desc->buffer_offset;
 
-       radeon_emit(cs, PKT3(PKT3_SET_SH_REG, 2, 0));
-       radeon_emit(cs, (sh_base + desc->shader_userdata_offset - 
SI_SH_REG_OFFSET) >> 2);
        radeon_emit(cs, va);
        radeon_emit(cs, va >> 32);
 }
 
+static void si_emit_shader_pointer(struct si_context *sctx,
+                                  struct si_descriptors *desc,
+                                  unsigned sh_base)
+{
+       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+
+       si_emit_shader_pointer_head(cs, desc, sh_base, 1);
+       si_emit_shader_pointer_body(cs, desc);
+}
+
 static void si_emit_global_shader_pointers(struct si_context *sctx,
                                           struct si_descriptors *descs)
 {
        if (sctx->b.chip_class == GFX9) {
                /* Broadcast it to all shader stages. */
                si_emit_shader_pointer(sctx, descs,
                                       R_00B530_SPI_SHADER_USER_DATA_COMMON_0);
                return;
        }
 
-- 
2.7.4

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