From: Marek Olšák <marek.ol...@amd.com>
i.e. don't use |=
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 19 +++++++++++++++----
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 +
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index d9d2a8b..0a657f7 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -718,34 +718,45 @@ static bool amdgpu_get_new_ib(struct radeon_winsys *ws,
struct amdgpu_cs *cs,
ib->used_ib_space + ib_size > ib->big_ib_buffer->size) {
if (!amdgpu_ib_new_buffer(aws, ib))
return false;
}
info->va_start = amdgpu_winsys_bo(ib->big_ib_buffer)->va +
ib->used_ib_space;
info->ib_bytes = 0;
/* ib_bytes is in dwords and the conversion to bytes will be done before
* the CS ioctl. */
ib->ptr_ib_size = &info->ib_bytes;
+ ib->ptr_ib_size_inside_ib = false;
amdgpu_cs_add_buffer(&cs->main.base, ib->big_ib_buffer,
RADEON_USAGE_READ, 0, RADEON_PRIO_IB1);
ib->base.current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
ib_size = ib->big_ib_buffer->size - ib->used_ib_space;
ib->base.current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs->ring_type);
return true;
}
+static void amdgpu_set_ib_size(struct amdgpu_ib *ib)
+{
+ if (ib->ptr_ib_size_inside_ib) {
+ *ib->ptr_ib_size = ib->base.current.cdw |
+ S_3F2_CHAIN(1) | S_3F2_VALID(1);
+ } else {
+ *ib->ptr_ib_size = ib->base.current.cdw;
+ }
+}
+
static void amdgpu_ib_finalize(struct amdgpu_ib *ib)
{
- *ib->ptr_ib_size |= ib->base.current.cdw;
+ amdgpu_set_ib_size(ib);
ib->used_ib_space += ib->base.current.cdw * 4;
ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw +
ib->base.current.cdw);
}
static bool amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
enum ring_type ring_type)
{
switch (ring_type) {
case RING_DMA:
cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_DMA;
@@ -926,28 +937,28 @@ static bool amdgpu_cs_check_space(struct radeon_winsys_cs
*rcs, unsigned dw)
assert(ib->used_ib_space + 4 * rcs->current.max_dw <=
ib->big_ib_buffer->size);
/* Pad with NOPs and add INDIRECT_BUFFER packet */
while ((rcs->current.cdw & 7) != 4)
radeon_emit(rcs, 0xffff1000); /* type3 nop packet */
radeon_emit(rcs, PKT3(ib->ib_type == IB_MAIN ? PKT3_INDIRECT_BUFFER_CIK
: PKT3_INDIRECT_BUFFER_CONST, 2,
0));
radeon_emit(rcs, va);
radeon_emit(rcs, va >> 32);
- new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw];
- radeon_emit(rcs, S_3F2_CHAIN(1) | S_3F2_VALID(1));
+ new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++];
assert((rcs->current.cdw & 7) == 0);
assert(rcs->current.cdw <= rcs->current.max_dw);
- *ib->ptr_ib_size |= rcs->current.cdw;
+ amdgpu_set_ib_size(ib);
ib->ptr_ib_size = new_ptr_ib_size;
+ ib->ptr_ib_size_inside_ib = true;
/* Hook up the new chunk */
rcs->prev[rcs->num_prev].buf = rcs->current.buf;
rcs->prev[rcs->num_prev].cdw = rcs->current.cdw;
rcs->prev[rcs->num_prev].max_dw = rcs->current.cdw; /* no modifications */
rcs->num_prev++;
ib->base.prev_dw += ib->base.current.cdw;
ib->base.current.cdw = 0;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 21e1354..1c3d0f0 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -66,20 +66,21 @@ enum ib_type {
struct amdgpu_ib {
struct radeon_winsys_cs base;
/* A buffer out of which new IBs are allocated. */
struct pb_buffer *big_ib_buffer;
uint8_t *ib_mapped;
unsigned used_ib_space;
unsigned max_ib_size;
uint32_t *ptr_ib_size;
+ bool ptr_ib_size_inside_ib;
enum ib_type ib_type;
};
struct amdgpu_cs_context {
struct drm_amdgpu_cs_chunk_ib ib[IB_NUM];
/* Buffers. */
unsigned max_real_buffers;
unsigned num_real_buffers;
struct amdgpu_cs_buffer *real_buffers;
--
2.7.4
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