On Wed, May 3, 2017 at 2:22 AM, Topi Pohjolainen <topi.pohjolai...@gmail.com
> wrote:
> leaving y-tiled (r8stencil) copies still as they were.
>
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 24 +++++++----
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 57
> ---------------------------
> src/mesa/drivers/dri/i965/gen6_depth_state.c | 31 +++++++--------
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 ++++++++++++++-------
> 4 files changed, 63 insertions(+), 94 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 158cf66..7b6c13d 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -146,8 +146,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
> .write_domain = is_render_target ? I915_GEM_DOMAIN_RENDER : 0,
> };
>
> - if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8 &&
> - mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
> + if (brw->gen == 6 && mt->format == MESA_FORMAT_S_UINT8) {
> /* Sandy bridge stencil and HiZ use this ALL_SLICES_AT_EACH_LOD
> hack in
> * order to allow for layered rendering. The hack makes each LOD
> of the
> * stencil or HiZ buffer a single tightly packed array surface at
> some
> @@ -166,12 +165,23 @@ blorp_surf_for_miptree(struct brw_context *brw,
> * consulted. Otherwise surf is ignored and there is no need to
> adjust
> * it any further. See blorp_emit_depth_stencil_config().
> */
> - surf->addr.offset += brw_stencil_all_slices_at_each_lod_offset(
> - surf->surf, *level);
> + uint32_t x_offset_sa, y_offset_sa;
> + get_image_offset_sa_gen6_back_to_back(
> + &mt->surf, *level, 0, 0, &x_offset_sa, &y_offset_sa);
> + assert(x_offset_sa == 0);
> +
> + /* The stencil buffer has quirky pitch requirements. From Vol 2a,
> + * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
> + * The pitch must be set to 2x the value computed based on
> width, as
> + * the stencil buffer is stored with two rows interleaved.
> + *
> + * As ISL uses twice the width, byte offset calculation needs to use
> + * half of that.
> + */
> + const uint32_t offset = y_offset_sa * mt->surf.row_pitch / 2;
>
If you used isl_tiling_get_intratile_offset_sa, it would take care of this
for you because it does a trip through logical tile sizes.
> + assert(offset % 4096 == 0);
>
> - assert(brw_stencil_all_slices_at_each_lod_offset(surf->surf,
> *level) ==
> - mt->level[*level].level_y * mt->pitch +
> - mt->level[*level].level_x * 64);
> + surf->addr.offset += offset;
>
> *level = 0;
> }
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index deac692..dec04d7 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -163,63 +163,6 @@ gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
> }
> }
>
> -static unsigned
> -all_slices_at_each_lod_x_offset(unsigned w0, unsigned align, unsigned
> level)
> -{
> - const unsigned w = level >= 2 ? minify(w0, 1) : 0;
> - return ALIGN(w, align);
> -}
> -
> -static unsigned
> -all_slices_at_each_lod_y_offset(const struct isl_extent4d
> *phys_level0_sa,
> - enum isl_surf_dim dim, unsigned align,
> - unsigned level)
> -{
> - unsigned y = 0;
> -
> - /* Add vertical space taken by lower levels one by one. Levels one and
> two
> - * are side-by-side just below level zero. Levels three and greater are
> - * stacked one after another below level two.
> - */
> - for (unsigned i = 1; i <= level; ++i) {
> - const unsigned d = dim == ISL_SURF_DIM_3D ?
> - minify(phys_level0_sa->depth, i - 1) :
> - phys_level0_sa->array_len;
> -
> - /* Levels two and greater are stacked just below level zero. */
> - if (i != 2) {
> - const unsigned h = minify(phys_level0_sa->height, i - 1);
> - y += d * ALIGN(h, align);
> - }
> - }
> -
> - return y;
> -}
> -
> -uint32_t
> -brw_stencil_all_slices_at_each_lod_offset(const struct isl_surf *surf,
> - unsigned level)
> -{
> - const unsigned halign = 64;
> - const unsigned valign = 64;
> - const unsigned level_x = all_slices_at_each_lod_x_offset(
> - surf->phys_level0_sa.width, halign, level);
> - const unsigned level_y = all_slices_at_each_lod_y_offset(
> - &surf->phys_level0_sa, surf->dim, valign, level);
> -
> - /* From Vol 2a, 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface
> Pitch":
> - * The pitch must be set to 2x the value computed based on width, as
> - * the stencil buffer is stored with two rows interleaved.
> - *
> - * While ISL surface stores the pitch expected by hardware, the offset
> - * into individual slices needs to be calculated as if rows are
> - * interleaved.
> - */
> - const unsigned two_rows_interleaved_pitch = surf->row_pitch / 2;
> -
> - return level_y * two_rows_interleaved_pitch + level_x * 64;
> -}
> -
> uint32_t
> brw_get_mipmap_total_width(unsigned w0, unsigned num_levels, unsigned
> halign)
> {
> diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> index 16fb209..1850934 100644
> --- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
> @@ -189,29 +189,28 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
>
> /* Emit stencil buffer. */
> if (separate_stencil) {
> - uint32_t offset = 0;
> + assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
>
> - if (stencil_mt->array_layout == ALL_SLICES_AT_EACH_LOD) {
> - assert(stencil_mt->format == MESA_FORMAT_S_UINT8);
> -
> - struct isl_surf temp_surf;
> - intel_miptree_get_isl_surf(brw, stencil_mt, &temp_surf);
> -
> - offset = brw_stencil_all_slices_at_each_lod_offset(
> - &temp_surf, lod);
> - assert(offset ==
> - stencil_mt->level[lod].level_y * stencil_mt->pitch +
> - stencil_mt->level[lod].level_x * 64);
> - }
> + uint32_t x_offset_sa, y_offset_sa;
> + get_image_offset_sa_gen6_back_to_back(&stencil_mt->surf,
> + lod, 0, 0,
> + &x_offset_sa,
> &y_offset_sa);
>
Why are you calling this directly and not just using
isl_surf_get_image_offset_sa?
> + assert(x_offset_sa == 0);
>
> - BEGIN_BATCH(3);
> - OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
> /* The stencil buffer has quirky pitch requirements. From Vol
> 2a,
> * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
> * The pitch must be set to 2x the value computed based on
> width, as
> * the stencil buffer is stored with two rows interleaved.
> + *
> + * As ISL uses twice the width, byte offset calculation needs to
> use
> + * half of that.
> */
> - OUT_BATCH(2 * stencil_mt->pitch - 1);
> + const uint32_t offset = y_offset_sa * stencil_mt->surf.row_pitch
> / 2;
>
Again, use isl_tiling_get_intratile_offset_sa
> + assert(offset % 4096 == 0);
> +
> + BEGIN_BATCH(3);
> + OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
> + OUT_BATCH(stencil_mt->surf.row_pitch - 1);
> OUT_RELOC(stencil_mt->bo,
> I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
> offset);
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index ced1e0e..febe880 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -678,6 +678,14 @@ miptree_create(struct brw_context *brw,
> GLuint num_samples,
> uint32_t layout_flags)
> {
> + if (format == MESA_FORMAT_S_UINT8)
> + return make_surface(brw, target, format, first_level, last_level,
> + width0, height0, depth0, num_samples,
> + ISL_TILING_W,
> + ISL_SURF_USAGE_STENCIL_BIT |
> + ISL_SURF_USAGE_TEXTURE_BIT,
> + BO_ALLOC_FOR_RENDER);
> +
> struct intel_mipmap_tree *mt;
> mesa_format tex_format = format;
> mesa_format etc_format = MESA_FORMAT_NONE;
> @@ -2275,28 +2283,35 @@ intel_update_r8stencil(struct brw_context *brw,
> !src->r8stencil_needs_update)
> return;
>
> + assert(src->surf.size > 0);
> +
> if (!mt->r8stencil_mt) {
> const uint32_t r8stencil_flags =
> MIPTREE_LAYOUT_ACCELERATED_UPLOAD | MIPTREE_LAYOUT_TILING_Y |
> MIPTREE_LAYOUT_DISABLE_AUX;
> assert(brw->gen > 6); /* Handle MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD
> */
> - mt->r8stencil_mt = intel_miptree_create(brw,
> - src->target,
> - MESA_FORMAT_R_UINT8,
> - src->first_level,
> - src->last_level,
> - src->logical_width0,
> - src->logical_height0,
> - src->logical_depth0,
> - src->num_samples,
> - r8stencil_flags);
> + mt->r8stencil_mt = intel_miptree_create(
> + brw,
> + src->target,
> + MESA_FORMAT_R_UINT8,
> + 0, src->surf.levels - 1,
> + src->surf.logical_level0_px.width,
> + src->surf.logical_level0_px.height,
> + src->surf.dim_layout ==
> ISL_DIM_LAYOUT_GEN4_3D ?
> + src->surf.logical_level0_px.depth :
> + src->surf.logical_level0_px.array_len,
> + src->surf.samples,
> + r8stencil_flags);
> assert(mt->r8stencil_mt);
> }
>
> struct intel_mipmap_tree *dst = mt->r8stencil_mt;
>
> - for (int level = src->first_level; level <= src->last_level; level++) {
> - const unsigned depth = src->level[level].depth;
> + for (int level = 0; level < src->surf.levels; level++) {
> + const unsigned depth = src->surf.dim_layout ==
> ISL_DIM_LAYOUT_GEN4_3D ?
>
ISL_SURF_DIM_3D
> + minify(src->surf.logical_level0_px.depth, level) :
> + src->surf.logical_level0_px.array_len;
> +
> const int layers_per_blit =
> (dst->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
> dst->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
> @@ -2309,8 +2324,10 @@ intel_update_r8stencil(struct brw_context *brw,
> dst, level, layers_per_blit * layer,
> MESA_FORMAT_R_UNORM8,
> 0, 0,
> - minify(src->logical_width0, level),
> - minify(src->logical_height0, level),
> + minify(src->surf.logical_
> level0_px.width,
> + level),
> + minify(src->surf.logical_
> level0_px.height,
> + level),
> 0, 0,
> minify(dst->logical_width0, level),
> minify(dst->logical_height0, level),
> --
> 2.9.3
>
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