Also drops unnecessary check for stencil_mt when setting qpitch -
that is inside stencil_mt guarded block already.
Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/gen8_depth_state.c | 38 +++++++++++++++++++++++-----
1 file changed, 31 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c
b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 8210e7c..c06d13c 100644
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -51,6 +51,8 @@ emit_depth_packets(struct brw_context *brw,
uint32_t min_array_element)
{
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
+ unsigned depth_pitch = 0 + 1;
+ unsigned depth_qpitch = 0;
/* Skip repeated NULL depth/stencil emits (think 2D rendering). */
if (!depth_mt && !stencil_mt && brw->no_depth_or_stencil) {
@@ -60,6 +62,14 @@ emit_depth_packets(struct brw_context *brw,
brw_emit_depth_stall_flushes(brw);
+ if (depth_mt && depth_mt->surf.size > 0) {
+ depth_pitch = depth_mt->surf.row_pitch;
+ depth_qpitch = depth_mt->surf.array_pitch_el_rows;
+ } else if (depth_mt) {
+ depth_pitch = depth_mt->pitch;
+ depth_qpitch = depth_mt->qpitch;
+ }
+
/* _NEW_BUFFERS, _NEW_DEPTH, _NEW_STENCIL */
BEGIN_BATCH(8);
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (8 - 2));
@@ -68,7 +78,7 @@ emit_depth_packets(struct brw_context *brw,
(stencil_mt != NULL && stencil_writable) << 27 |
(hiz ? 1 : 0) << 22 |
depthbuffer_format << 18 |
- (depth_mt ? depth_mt->pitch - 1 : 0));
+ (depth_pitch - 1));
if (depth_mt) {
OUT_RELOC64(depth_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
@@ -79,7 +89,7 @@ emit_depth_packets(struct brw_context *brw,
OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod);
OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | mocs_wb);
OUT_BATCH(0);
- OUT_BATCH(((depth - 1) << 21) | (depth_mt ? depth_mt->qpitch >> 2 : 0));
+ OUT_BATCH(((depth - 1) << 21) | (depth_qpitch >> 2));
ADVANCE_BATCH();
if (!hiz) {
@@ -113,6 +123,17 @@ emit_depth_packets(struct brw_context *brw,
if (intel_miptree_wants_r8_stencil(brw))
stencil_mt->r8stencil_needs_update = true;
+ unsigned stencil_pitch = 0 + 1;
+ unsigned stencil_qpitch = 0;
+
+ if (stencil_mt->surf.size > 0) {
+ stencil_pitch = stencil_mt->surf.row_pitch;
+ stencil_qpitch = stencil_mt->surf.array_pitch_el_rows;
+ } else {
+ stencil_pitch = 2 * stencil_mt->pitch;
+ stencil_qpitch = stencil_mt->qpitch;
+ }
+
BEGIN_BATCH(5);
OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (5 - 2));
/* The stencil buffer has quirky pitch requirements. From the Graphics
@@ -129,11 +150,10 @@ emit_depth_packets(struct brw_context *brw,
* page (which would imply that it does). Experiments with the hardware
* indicate that it does.
*/
- OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 |
- (2 * stencil_mt->pitch - 1));
+ OUT_BATCH(HSW_STENCIL_ENABLED | mocs_wb << 22 | (stencil_pitch - 1));
OUT_RELOC64(stencil_mt->bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(stencil_mt ? stencil_mt->qpitch >> 2 : 0);
+ OUT_BATCH(stencil_qpitch >> 2);
ADVANCE_BATCH();
}
@@ -193,7 +213,8 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
break;
case GL_TEXTURE_3D:
assert(mt);
- depth = MAX2(mt->logical_depth0, 1);
+ depth = mt->surf.size > 0 ? mt->surf.logical_level0_px.depth :
+ MAX2(mt->logical_depth0, 1);
surftype = translate_tex_target(gl_target);
break;
case GL_TEXTURE_1D_ARRAY:
@@ -216,7 +237,10 @@ gen8_emit_depth_stencil_hiz(struct brw_context *brw,
lod = irb ? irb->mt_level - irb->mt->first_level : 0;
- if (mt) {
+ if (mt && mt->surf.size > 0) {
+ width = mt->surf.logical_level0_px.width;
+ height = mt->surf.logical_level0_px.height;
+ } else if (mt) {
width = mt->logical_width0;
height = mt->logical_height0;
}
--
2.9.3
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