On Wed, May 3, 2017 at 2:22 AM, Topi Pohjolainen <topi.pohjolai...@gmail.com > wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- > src/intel/isl/isl_gen7.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c > index 18687b5..cf5b377 100644 > --- a/src/intel/isl/isl_gen7.c > +++ b/src/intel/isl/isl_gen7.c > @@ -375,7 +375,11 @@ gen7_choose_valign_el(const struct isl_device *dev, > * FINISHME(chadv): Decide to set valign=4 or valign=8 after isl's > API > * is more polished. > */ > - require_valign4 = true; > + > + /* Using valign 4 upsets all depthstencil-render-miplevels on IVB > and > + * HSW. Use alignment 8 instead. > + */ > + return 8; > I'm confused. This seems to contradict the documentation which says that valign for depth is hard-coded to 4 in the hardware.
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