On Mon, 5 Dec 2011 14:24:08 -0800, Paul Berry <stereotype...@gmail.com> wrote:
> On 5 December 2011 11:54, Kenneth Graunke <kenn...@whitecape.org> wrote:
>
> > On 12/05/2011 09:40 AM, Paul Berry wrote:
> > > Normally when outputting instructions in SPF (single program flow)
> > > mode, we convert IF and ELSE instructions to conditional ADD
> > > instructions applied to the IP register, since this lets us avoid
> > > having to emit an ENDIF instruction (and, in Gen4, lets us avoid using
> > > up precious space in the MaskStack).
> > >
> > > However, according to the SandyBridge PRM (Volume 4 part 2, p79):
> > >
> > > [Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by
> > > non-flow control instructions.
> > >
> > > So we have to disable this optimization on Gen6.
> > >
> > > The reason we never noticed this problem before is that so far we
> > > haven't needed to use SPF mode on Gen6. However, later patches in
> > > this series will introduce a Gen6 GS program which uses SPF mode.
> >
> > I'm wondering if this is broken on Gen7+ as well. It might be better to
> > just disable this optimization on intel->gen >= 6 altogether. I'm
> > honestly not sure it provides much benefit post-Ironlake.
> >
>
> > We could also test it on Ivybridge; if it works, I'm not opposed to
> > leaving it enabled either.
> >
>
> Yeah, I think you're right. My preference would be to just go ahead and
> disable the optimization on gen>=6 and be done with it; I don't think much
> would be gained from testing on IvyBridge at this point.I think with the elimination of thread switches on flow control with gen6+, the optimization isn't one any more with newer hardware. So I'm in favor of just dropping it on newer stuff and calling it good.
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