On 12/05/2011 09:40 AM, Paul Berry wrote:
> Normally when outputting instructions in SPF (single program flow)
> mode, we convert IF and ELSE instructions to conditional ADD
> instructions applied to the IP register, since this lets us avoid
> having to emit an ENDIF instruction (and, in Gen4, lets us avoid using
> up precious space in the MaskStack).
>
> However, according to the SandyBridge PRM (Volume 4 part 2, p79):
>
> [Errata DevSNB{WA}] - When SPF is ON, IP may not be updated by
> non-flow control instructions.
>
> So we have to disable this optimization on Gen6.
>
> The reason we never noticed this problem before is that so far we
> haven't needed to use SPF mode on Gen6. However, later patches in
> this series will introduce a Gen6 GS program which uses SPF mode.
I'm wondering if this is broken on Gen7+ as well. It might be better to
just disable this optimization on intel->gen >= 6 altogether. I'm
honestly not sure it provides much benefit post-Ironlake.
We could also test it on Ivybridge; if it works, I'm not opposed to
leaving it enabled either.
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