On Mon, 21 Nov 2011 14:02:40 -0800, Chad Versace <chad.vers...@linux.intel.com>
wrote:
> Eric, is this v3 change what you had in mind?
>
> -----
>
> A lot of the state manipulation is handled by the meta-op state setup.
> However, some batches need manual intervention.
>
> v2:
> Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit
> for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets
> ctx->Depth.Test, just read the value from that.
>
> v3:
> Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it
> immediately before and after executing the HiZ operation in
> gen6_resolve_slice(). Add the flag to the the dirty bits for the
> following state packets:
> gen6_clip_state
> gen6_depth_stencil_state
> gen6_sf_state
> gen6_wm_state
>
> CC: Eric Anholt <e...@anholt.net>
> Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_context.h | 2 ++
> src/mesa/drivers/dri/i965/brw_draw.c | 9 ++++++++-
> src/mesa/drivers/dri/i965/gen6_clip_state.c | 20 +++++++++++++++++++-
> src/mesa/drivers/dri/i965/gen6_depthstencil.c | 11 ++++++++---
> src/mesa/drivers/dri/i965/gen6_sf_state.c | 18 +++++++++++++++---
> src/mesa/drivers/dri/i965/gen6_wm_state.c | 20 +++++++++++++++++++-
> 6 files changed, 71 insertions(+), 9 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h
> b/src/mesa/drivers/dri/i965/brw_context.h
> index fa2fc72..ec05fb7 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -144,6 +144,7 @@ enum brw_state_id {
> BRW_STATE_VS_CONSTBUF,
> BRW_STATE_PROGRAM_CACHE,
> BRW_STATE_STATE_BASE_ADDRESS,
> + BRW_STATE_HIZ,
> };
>
> #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
> @@ -172,6 +173,7 @@ enum brw_state_id {
> #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
> #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
> #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
> +#define BRW_NEW_HIZ (1 << BRW_STATE_HIZ)
Hmm, I apparently didn't have a comment in brw_context.h mentioning this
requirement: when adding a new flag, it also need to go in the obvious
place in brw_state_upload.c for keeping INTEL_DEBUG=state working.
> @@ -89,7 +93,8 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
> const struct brw_tracked_state gen6_depth_stencil_state = {
> .dirty = {
> .mesa = _NEW_DEPTH | _NEW_STENCIL,
> - .brw = BRW_NEW_BATCH,
> + .brw = BRW_NEW_BATCH |
> + BRW_NEW_HIZ,
> .cache = 0,
> },
Nitpicky: throw some parens around that series of BRW_NEW_* to make them
line up.
Other than that,
Reviewed-by: Eric Anholt <e...@anholt.net>
pgpuQuW0i2Vkb.pgp
Description: PGP signature
_______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
