Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2001cf3..632f5f3 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -160,8 +160,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
* consulted. Otherwise surf is ignored and there is no need to adjust
* it any further. See blorp_emit_depth_stencil_config().
*/
- surf->addr.offset += (mt->level[*level].level_y * mt->pitch +
- mt->level[*level].level_x * 64);
+ surf->addr.offset += brw_stencil_all_slices_at_each_lod_offset(
+ surf->surf, mt, *level);
+
+ assert(brw_stencil_all_slices_at_each_lod_offset(
+ surf->surf, mt, *level) ==
+ mt->level[*level].level_y * mt->pitch +
+ mt->level[*level].level_x * 64);
+
*level = 0;
}
@@ -239,9 +245,14 @@ blorp_surf_for_miptree(struct brw_context *brw,
* surf->aux_surf.row_pitch in turn is set by
* intel_miptree_get_aux_isl_surf().
*/
- surf->aux_addr.offset = intel_miptree_get_aligned_offset(hiz_mt,
- hiz_mt->level[*level].level_x,
- hiz_mt->level[*level].level_y);
+ surf->aux_addr.offset = brw_hiz_all_slices_at_each_lod_offset(
+ &surf->surf->phys_level0_sa, surf->surf->dim,
+ surf->surf->levels, surf->surf->format, hiz_mt, *level);
+ assert(surf->aux_addr.offset ==
+ intel_miptree_get_aligned_offset(
+ hiz_mt,
+ hiz_mt->level[*level].level_x,
+ hiz_mt->level[*level].level_y));
assert(hiz_mt->pitch == aux_surf->row_pitch);
}
}
--
2.5.5
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