Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 67 ++++++++++++++++-----------
1 file changed, 41 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 3914506..cdfd49d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1509,6 +1509,43 @@ intel_mcs_miptree_buf_create(struct brw_context *brw,
return buf;
}
+static struct intel_miptree_aux_buffer *
+intel_alloc_aux_buffer(struct brw_context *brw,
+ const char *name,
+ const struct isl_surf *main_surf,
+ const struct isl_surf *aux_surf,
+ uint32_t alloc_flags,
+ struct intel_mipmap_tree *mt)
+{
+ struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
+ if (!buf)
+ return false;
+
+ buf->size = aux_surf->size;
+ buf->pitch = aux_surf->row_pitch;
+ buf->qpitch = isl_surf_get_array_pitch_sa_rows(aux_surf);
+
+ uint32_t tiling = I915_TILING_Y;
+ unsigned long pitch;
+
+ /* ISL has stricter set of alignment rules then the drm allocator.
+ * Therefore one can pass the ISL dimensions in terms of bytes instead of
+ * trying to recalculate based on different format block sizes.
+ */
+ buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, name,
+ buf->pitch, buf->size / buf->pitch,
+ 1, &tiling, &pitch, alloc_flags);
+ if (buf->bo) {
+ assert(pitch == buf->pitch);
+ assert(tiling == I915_TILING_Y);
+ } else {
+ free(buf);
+ return false;
+ }
+
+ return buf;
+}
+
static bool
intel_miptree_alloc_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
@@ -1590,14 +1627,6 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
assert(temp_ccs_surf.size &&
(temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
- struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
- if (!buf)
- return false;
-
- buf->size = temp_ccs_surf.size;
- buf->pitch = temp_ccs_surf.row_pitch;
- buf->qpitch = isl_surf_get_array_pitch_sa_rows(&temp_ccs_surf);
-
/* In case of compression mcs buffer needs to be initialised requiring the
* buffer to be immediately mapped to cpu space for writing. Therefore do
* not use the gpu access flag which can cause an unnecessary delay if the
@@ -1605,25 +1634,11 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context
*brw,
*/
const uint32_t alloc_flags =
is_lossless_compressed ? 0 : BO_ALLOC_FOR_RENDER;
- uint32_t tiling = I915_TILING_Y;
- unsigned long pitch;
-
- /* ISL has stricter set of alignment rules then the drm allocator.
- * Therefore one can pass the ISL dimensions in terms of bytes instead of
- * trying to recalculate based on different format block sizes.
- */
- buf->bo = drm_intel_bo_alloc_tiled(brw->bufmgr, "ccs-miptree",
- buf->pitch, buf->size / buf->pitch,
- 1, &tiling, &pitch, alloc_flags);
- if (buf->bo) {
- assert(pitch == buf->pitch);
- assert(tiling == I915_TILING_Y);
- } else {
- free(buf);
+ mt->mcs_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
+ &temp_main_surf, &temp_ccs_surf,
+ alloc_flags, mt);
+ if (!mt->mcs_buf)
return false;
- }
-
- mt->mcs_buf = buf;
/* From Gen9 onwards single-sampled (non-msrt) auxiliary buffers are
* used for lossless compression which requires similar initialisation
--
2.5.5
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