This series is a step towards using ISL instead of current intel_mipnap_tree/brw_tex_layout logic in i965. First 11 patches simplify the workspace for the rest and more functional changes.
Next seven patches introduce simple on-demand calculators for stencil and hiz offsets on gen6. On gen6 hardware doesn't support mipmaps for stencil or hiz. Driver works around this by offsetting hiz/stencil surfaces to desired level-of-detail. Current logic relies on pre-computed offset table which is replaced by helpers functions calculating the offsets when needed. This drops dependency to intel_mipnap_tree. Patch 22 prepares ISL to provide large enough auxiliary size for MCS on gen7 and on gen8. I started seeing intermittent failures (once in 10 subsequent runs) with "texelFetch fs sampler2DMSArray 4 98x1x9-98x129x9 -auto -fbo" with IVB, HSW and BDW, but not with SKL. After some debugging I tracked this down to SKL using vertical alignment of four requiring 4608 bytes (and driver allocated two pages). Earlier gens used vertical alignment of one and only allocated one page. More details in the patch. I included patch 21 for consistency sake as to me it seems we are missing something of that sort. Patch 23 starts using ISL for MCS and the rest for HIZ. I tried to make individual steps as small as possible adding temporary asserts checking that newly added calculations matched the current. Topi Pohjolainen (27): i965/meta: Remove unused brw_get_rb_for_slice() i965/miptree: Remove redundant check for null texture i965: Remove check for hiz on earlier gens than SNB i965/gen6: Remove check for stencil format i965: Replace open coded with intel_miptree_get_image_offset() i965/blorp/gen6: Simplify hiz surface setup i965/gen6: Simplify hiz surface setup i965/blorp/gen6: Remove dead code in hiz setup i965/gen6: Remove dead code in hiz surface setup i965/blorp/gen6: Drop unnecessary stencil/hiz surf dimension adjust i965/hiz/gen6: Stop setting false qpitch i965/gen6: Calculate stencil offset on demand i965/gen6: Calculate hiz offset on demand i965/blorp/gen6: Use on-demand stencil/hiz offset resolvers i965/gen6: Drop miptrees in depth/stencil offset resolvers i965/blorp/gen6: Set aux pitch directly i965/gen6/hiz: Add direct buffer size resolver i965/gen6: Allocate hiz directly without miptree i965/miptree: Refactor aux surface allocation i965/miptree: Refactor ISL aux usage resolver intel/isl/gen7: Add CCS alignment restrictions intel/isl: Apply render target alignment constraints for MCS i965/miptree: Use ISL for MCS layouts i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init i965/miptree/gen7+: Use ISL for HIZ layouts i965/blorp: Use hiz surface instead of creating copy i965: Use stored hiz surface instead of creating copy src/intel/isl/isl_gen7.c | 55 +++ src/intel/isl/isl_gen8.c | 16 + src/intel/isl/isl_gen9.c | 16 + src/mesa/drivers/dri/i965/brw_blorp.c | 108 ++--- src/mesa/drivers/dri/i965/brw_context.h | 6 - src/mesa/drivers/dri/i965/brw_meta_util.c | 44 -- src/mesa/drivers/dri/i965/brw_meta_util.h | 5 - src/mesa/drivers/dri/i965/brw_misc_state.c | 23 +- src/mesa/drivers/dri/i965/brw_tex_layout.c | 131 ++++++ src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13 +- src/mesa/drivers/dri/i965/gen6_depth_state.c | 45 +- src/mesa/drivers/dri/i965/gen7_misc_state.c | 5 +- src/mesa/drivers/dri/i965/gen8_depth_state.c | 6 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 548 ++++++----------------- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 45 +- src/mesa/drivers/dri/i965/intel_pixel_read.c | 16 +- 16 files changed, 472 insertions(+), 610 deletions(-) -- 2.5.5 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
