On Tue, Oct 11, 2016 at 12:26 PM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 14 ++++++++------
> src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++-
> src/mesa/drivers/dri/i965/brw_context.c | 16 +++++++++++-----
> src/mesa/drivers/dri/i965/intel_blit.c | 8 ++++++--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 27
> +++++++++++++++++++++++++--
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 1 +
> 6 files changed, 53 insertions(+), 16 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
> b/src/mesa/drivers/dri/i965/brw_blorp.c
> index 4030038..c55bbc8 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.c
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.c
> @@ -324,7 +324,8 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
> * to destination color buffers, and the standard render path is
> * fast-color-aware.
> */
> - intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
> + intel_miptree_resolve_color(brw, src_mt, src_level, src_logical_layer,
> + INTEL_MIPTREE_IGNORE_CCS_E);
> intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
> intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
>
> @@ -409,7 +410,8 @@ brw_blorp_copy_miptrees(struct brw_context *brw,
> * to destination color buffers, and the standard render path is
> * fast-color-aware.
> */
> - intel_miptree_resolve_color(brw, src_mt, INTEL_MIPTREE_IGNORE_CCS_E);
> + intel_miptree_resolve_color(brw, src_mt, src_level, src_layer,
> + INTEL_MIPTREE_IGNORE_CCS_E);
> intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
> intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
>
> @@ -918,22 +920,22 @@ brw_blorp_clear_color(struct brw_context *brw,
> struct gl_framebuffer *fb,
> }
>
> void
> -brw_blorp_resolve_color(struct brw_context *brw, struct
> intel_mipmap_tree *mt)
> +brw_blorp_resolve_color(struct brw_context *brw, struct
> intel_mipmap_tree *mt,
> + unsigned level, unsigned layer)
> {
> DBG("%s to mt %p\n", __FUNCTION__, mt);
>
> const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
>
> - intel_miptree_check_level_layer(mt, 0 /* level */, 0 /* layer */);
> + intel_miptree_check_level_layer(mt, level, layer);
>
> struct isl_surf isl_tmp[2];
> struct blorp_surf surf;
> - unsigned level = 0;
> blorp_surf_for_miptree(brw, &surf, mt, true, &level, isl_tmp);
>
> struct blorp_batch batch;
> blorp_batch_init(&brw->blorp, &batch, brw);
> - blorp_ccs_resolve(&batch, &surf, 0 /* level */, 0 /* layer */,
> + blorp_ccs_resolve(&batch, &surf, level, layer,
> brw_blorp_to_isl_format(brw, format, true));
> blorp_batch_finish(&batch);
>
> diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
> b/src/mesa/drivers/dri/i965/brw_blorp.h
> index abf3956..ca0a5dd 100644
> --- a/src/mesa/drivers/dri/i965/brw_blorp.h
> +++ b/src/mesa/drivers/dri/i965/brw_blorp.h
> @@ -64,7 +64,8 @@ brw_blorp_clear_color(struct brw_context *brw, struct
> gl_framebuffer *fb,
>
> void
> brw_blorp_resolve_color(struct brw_context *brw,
> - struct intel_mipmap_tree *mt);
> + struct intel_mipmap_tree *mt,
> + unsigned level, unsigned layer);
>
There's a tab hiding out in here.
>
> void
> intel_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 424469c..e1dec45 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -313,8 +313,11 @@ intel_update_state(struct gl_context * ctx, GLuint
> new_state)
> intel_renderbuffer(fb->_ColorDrawBuffers[i]);
>
> if (irb &&
> - intel_miptree_resolve_color(brw, irb->mt,
> - INTEL_MIPTREE_IGNORE_CCS_E))
> + intel_miptree_resolve_color(
> + brw, irb->mt, irb->mt_level,
> + intel_miptree_physical_to_logical_layer(
> + irb->mt, irb->mt_layer),
> + INTEL_MIPTREE_IGNORE_CCS_E))
> brw_render_cache_set_check_flush(brw, irb->mt->bo);
> }
> }
> @@ -1344,10 +1347,13 @@ intel_resolve_for_dri2_flush(struct brw_context
> *brw,
> rb = intel_get_renderbuffer(fb, buffers[i]);
> if (rb == NULL || rb->mt == NULL)
> continue;
> - if (rb->mt->num_samples <= 1)
> - intel_miptree_resolve_color(brw, rb->mt, 0);
> - else
> + if (rb->mt->num_samples <= 1) {
> + assert(rb->mt_layer == 0 && rb->mt_level == 0 &&
> + rb->layer_count == 1);
> + intel_miptree_resolve_color(brw, rb->mt, 0, 0, 0);
> + } else {
> intel_renderbuffer_downsample(brw, rb);
> + }
> }
> }
>
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
> b/src/mesa/drivers/dri/i965/intel_blit.c
> index b7a9cc9..8da863a 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -258,8 +258,12 @@ intel_miptree_blit(struct brw_context *brw,
> */
> intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_slice);
> intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
> - intel_miptree_resolve_color(brw, src_mt, 0);
> - intel_miptree_resolve_color(brw, dst_mt, 0);
> + intel_miptree_resolve_color(
> + brw, src_mt, src_level,
> + intel_miptree_physical_to_logical_layer(src_mt, src_slice), 0);
> + intel_miptree_resolve_color(
> + brw, dst_mt, dst_level,
> + intel_miptree_physical_to_logical_layer(dst_mt, dst_slice), 0);
>
> if (src_flip)
> src_y = minify(src_mt->physical_height0, src_level -
> src_mt->first_level) - src_y - height;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 9287d79..ce72e2c 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2099,12 +2099,35 @@ intel_miptree_all_slices_resolve_depth(struct
> brw_context *brw,
> BLORP_HIZ_OP_DEPTH_RESOLVE);
> }
>
> +static void
> +intel_miptree_check_color_resolve(const struct intel_mipmap_tree *mt,
> + unsigned level, unsigned layer)
> +{
> + if (!mt->mcs_mt)
> + return;
> +
> + /* Fast color clear is not supported for mipmapped surfaces. */
> + assert(level == 0 && mt->first_level == 0 && mt->last_level == 0);
> +
> + /* Compression of arrayed msaa surfaces is supported. */
> + if (mt->num_samples > 1)
> + return;
> +
> + /* Fast color clear is not supported for non-msaa arrays. */
> + assert(layer == 0 && mt->logical_depth0 == 1);
> +
> + (void)level;
> + (void)layer;
> +}
>
> bool
> intel_miptree_resolve_color(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> + unsigned level, unsigned layer,
> int flags)
> {
> + intel_miptree_check_color_resolve(mt, level, layer);
> +
> /* From gen9 onwards there is new compression scheme for single sampled
> * surfaces called "lossless compressed". These don't need to be always
> * resolved.
> @@ -2123,7 +2146,7 @@ intel_miptree_resolve_color(struct brw_context *brw,
> /* Fast color clear resolves only make sense for non-MSAA buffers.
> */
> if (mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE ||
> intel_miptree_is_lossless_compressed(brw, mt)) {
> - brw_blorp_resolve_color(brw, mt);
> + brw_blorp_resolve_color(brw, mt, level, layer);
> return true;
> } else {
> return false;
> @@ -2138,7 +2161,7 @@ intel_miptree_all_slices_resolve_color(struct
> brw_context *brw,
> struct intel_mipmap_tree *mt,
> int flags)
> {
> - intel_miptree_resolve_color(brw, mt, flags);
> + intel_miptree_resolve_color(brw, mt, 0, 0, flags);
> }
>
> /**
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> index 69f7c5d..bfb8ad5 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
> @@ -976,6 +976,7 @@ intel_miptree_used_for_rendering(const struct
> brw_context *brw,
> bool
> intel_miptree_resolve_color(struct brw_context *brw,
> struct intel_mipmap_tree *mt,
> + unsigned level, unsigned layer,
> int flags);
>
> void
> --
> 2.5.5
>
> _______________________________________________
> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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