Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.78 -> 1.79
TargetInstrInfo.h updated: 1.90 -> 1.91
---
Log message:
Use an enumeration to eliminate data relocations.
---
Diffs of the changes: (+19 -18)
MRegisterInfo.h | 18 +++++++++++++++---
TargetInstrInfo.h | 19 ++++---------------
2 files changed, 19 insertions(+), 18 deletions(-)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.78
llvm/include/llvm/Target/MRegisterInfo.h:1.79
--- llvm/include/llvm/Target/MRegisterInfo.h:1.78 Wed Jul 19 00:58:18 2006
+++ llvm/include/llvm/Target/MRegisterInfo.h Fri Jul 21 15:57:35 2006
@@ -49,6 +49,7 @@
typedef const MVT::ValueType* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
private:
+ unsigned ID;
bool isSubClass;
const vt_iterator VTs;
const sc_iterator SubClasses;
@@ -56,14 +57,18 @@
const unsigned RegSize, Alignment; // Size & Alignment of register in
bytes
const iterator RegsBegin, RegsEnd;
public:
- TargetRegisterClass(const MVT::ValueType *vts,
+ TargetRegisterClass(unsigned id,
+ const MVT::ValueType *vts,
const TargetRegisterClass * const *subcs,
const TargetRegisterClass * const *supcs,
unsigned RS, unsigned Al, iterator RB, iterator RE)
- : VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+ : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
-
+
+ // getID() - Return the register class ID number.
+ unsigned getID() const { return ID; }
+
// begin/end - Return all of the registers in this class.
iterator begin() const { return RegsBegin; }
iterator end() const { return RegsEnd; }
@@ -300,6 +305,13 @@
unsigned getNumRegClasses() const {
return regclass_end()-regclass_begin();
}
+
+ /// getRegClass - Returns the register class associated with the enumeration
+ /// value. See class TargetOperandInfo.
+ const TargetRegisterClass *getRegClass(unsigned i) const {
+ assert(i <= getNumRegClasses() && "Register Class ID out of range");
+ return i ? RegClassBegin[i - 1] : NULL;
+ }
//===--------------------------------------------------------------------===//
// Interfaces used by the register allocator and stack frame
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.90
llvm/include/llvm/Target/TargetInstrInfo.h:1.91
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.90 Fri Jun 16 20:42:20 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h Fri Jul 21 15:57:35 2006
@@ -90,10 +90,10 @@
///
class TargetOperandInfo {
public:
- /// RegClass - This specifies the register class of the operand if the
- /// operand is a register. If not, this contains null.
- const TargetRegisterClass *RegClass;
- unsigned Flags;
+ /// RegClass - This specifies the register class enumeration of the operand
+ /// if the operand is a register. If not, this contains 0.
+ unsigned short RegClass;
+ unsigned short Flags;
/// Currently no other information.
};
@@ -146,17 +146,6 @@
return get(Opcode).Name;
}
- const TargetRegisterClass
- *getInstrOperandRegClass(const TargetInstrDescriptor *II, unsigned Op) const
{
- if (Op >= II->numOperands) {
- assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of
instruction");
- return NULL;
- }
- const TargetOperandInfo &toi = II->OpInfo[Op];
- return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
- ? getPointerRegClass() : toi.RegClass;
- }
-
int getNumOperands(MachineOpCode Opcode) const {
return get(Opcode).numOperands;
}
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