Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAG.cpp updated: 1.98 -> 1.99
ScheduleDAGRRList.cpp updated: 1.8 -> 1.9
---
Log message:
Use an enumeration to eliminate data relocations.
---
Diffs of the changes: (+24 -7)
ScheduleDAG.cpp | 29 +++++++++++++++++++++++------
ScheduleDAGRRList.cpp | 2 +-
2 files changed, 24 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.98
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.99
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.98 Tue Jul 11 13:25:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Fri Jul 21 15:57:35 2006
@@ -226,7 +226,22 @@
return N;
}
-static unsigned CreateVirtualRegisters(MachineInstr *MI,
+static const TargetRegisterClass *getInstrOperandRegClass(
+ const MRegisterInfo *MRI,
+ const TargetInstrInfo *TII,
+ const TargetInstrDescriptor *II,
+ unsigned Op) {
+ if (Op >= II->numOperands) {
+ assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
+ return NULL;
+ }
+ const TargetOperandInfo &toi = II->OpInfo[Op];
+ return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
+ ? TII->getPointerRegClass() : MRI->getRegClass(toi.RegClass);
+}
+
+static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI,
+ MachineInstr *MI,
unsigned NumResults,
SSARegMap *RegMap,
const TargetInstrInfo *TII,
@@ -234,10 +249,10 @@
// Create the result registers for this node and add the result regs to
// the machine instruction.
unsigned ResultReg =
- RegMap->createVirtualRegister(TII->getInstrOperandRegClass(&II, 0));
+ RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0));
MI->addRegOperand(ResultReg, MachineOperand::Def);
for (unsigned i = 1; i != NumResults; ++i) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(&II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
assert(RC && "Isn't a register operand!");
MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def);
}
@@ -276,7 +291,8 @@
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II,
IIOpNum);
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
@@ -333,7 +349,8 @@
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
- const TargetRegisterClass *RC = TII->getInstrOperandRegClass(II,
IIOpNum);
+ const TargetRegisterClass *RC =
+ getInstrOperandRegClass(MRI, TII, II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegMap->getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
@@ -389,7 +406,7 @@
// Otherwise, create new virtual registers.
if (NumResults && VRBase == 0)
- VRBase = CreateVirtualRegisters(MI, NumResults, RegMap, TII, II);
+ VRBase = CreateVirtualRegisters(MRI, MI, NumResults, RegMap, TII, II);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.8
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.9
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.8 Wed Jun 28
18:17:23 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Fri Jul 21 15:57:35 2006
@@ -152,7 +152,7 @@
if (SU->Node->isTargetOpcode()) {
unsigned Opc = SU->Node->getTargetOpcode();
const TargetInstrDescriptor &II = TII->get(Opc);
- return II.OpInfo->RegClass;
+ return MRI->getRegClass(II.OpInfo->RegClass);
} else {
assert(SU->Node->getOpcode() == ISD::CopyFromReg);
unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
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