Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.134 -> 1.135
PPCISelLowering.h updated: 1.41 -> 1.42
PPCInstrAltivec.td updated: 1.43 -> 1.44
README_ALTIVEC.txt updated: 1.17 -> 1.18
---
Log message:
Pattern match vmrg* instructions, which are now lowered by the CFE into
shuffles.
---
Diffs of the changes: (+101 -12)
PPCISelLowering.cpp | 52 +++++++++++++++++++++++++++++++++++++++++++++++++---
PPCISelLowering.h | 8 ++++++++
PPCInstrAltivec.td | 50 ++++++++++++++++++++++++++++++++++++++++++++------
README_ALTIVEC.txt | 3 ---
4 files changed, 101 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.135
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.134 Thu Apr 6 13:26:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Thu Apr 6 16:11:54 2006
@@ -293,10 +293,50 @@
return true;
}
+/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
+/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
+bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR &&
+ N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
+ assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
+ "Unsupported merge size!");
+
+ for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
+ for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
+ if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
+ 8+j+i*UnitSize) ||
+ !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
+ 24+j+i*UnitSize))
+ return false;
+ }
+ return true;
+}
+
+/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
+/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
+bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR &&
+ N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
+ assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
+ "Unsupported merge size!");
+
+ for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
+ for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
+ if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
+ 0+j+i*UnitSize) ||
+ !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
+ 16+j+i*UnitSize))
+ return false;
+ }
+ return true;
+}
+
+
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
/// amount, otherwise return -1.
int PPC::isVSLDOIShuffleMask(SDNode *N) {
- assert(N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
+ assert(N->getOpcode() == ISD::BUILD_VECTOR &&
+ N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
// Find the first non-undef value in the shuffle mask.
unsigned i;
for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
@@ -833,13 +873,19 @@
if (V2.getOpcode() == ISD::UNDEF &&
(PPC::isSplatShuffleMask(PermMask.Val, 1) ||
PPC::isSplatShuffleMask(PermMask.Val, 2) ||
- PPC::isSplatShuffleMask(PermMask.Val, 4)))
+ PPC::isSplatShuffleMask(PermMask.Val, 4) ||
+ PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1))
return Op;
if (PPC::isVPKUWUMShuffleMask(PermMask.Val) ||
PPC::isVPKUHUMShuffleMask(PermMask.Val) ||
PPC::isVSLDOIShuffleMask(PermMask.Val) != -1 ||
- PPC::isVSLDOIRotateShuffleMask(PermMask.Val) != -1)
+ PPC::isVMRGLShuffleMask(PermMask.Val, 1) ||
+ PPC::isVMRGLShuffleMask(PermMask.Val, 2) ||
+ PPC::isVMRGLShuffleMask(PermMask.Val, 4) ||
+ PPC::isVMRGHShuffleMask(PermMask.Val, 1) ||
+ PPC::isVMRGHShuffleMask(PermMask.Val, 2) ||
+ PPC::isVMRGHShuffleMask(PermMask.Val, 4))
return Op;
// TODO: Handle more cases, and also handle cases that are cheaper to do as
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.42
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.41 Thu Apr 6 13:26:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Thu Apr 6 16:11:54 2006
@@ -109,6 +109,14 @@
/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
/// VPKUWUM instruction.
bool isVPKUWUMShuffleMask(SDNode *N);
+
+ /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
+ /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
+ bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize);
+
+ /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
+ /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
+ bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize);
/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
shift
/// amount, otherwise return -1.
Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
diff -u llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.43
llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.44
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td:1.43 Thu Apr 6 13:26:28 2006
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td Thu Apr 6 16:11:54 2006
@@ -24,6 +24,26 @@
return PPC::isVPKUWUMShuffleMask(N);
}]>;
+def VMRGLB_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isVMRGLShuffleMask(N, 1);
+}]>;
+def VMRGLH_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isVMRGLShuffleMask(N, 2);
+}]>;
+def VMRGLW_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isVMRGLShuffleMask(N, 4);
+}]>;
+def VMRGHB_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isVMRGHShuffleMask(N, 1);
+}]>;
+def VMRGHH_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isVMRGHShuffleMask(N, 2);
+}]>;
+def VMRGHW_shuffle_mask : PatLeaf<(build_vector), [{
+ return PPC::isVMRGHShuffleMask(N, 4);
+}]>;
+
+
def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N));
}]>;
@@ -278,12 +298,30 @@
def VMINUH : VX1_Int< 578, "vminuh", int_ppc_altivec_vminuh>;
def VMINUW : VX1_Int< 642, "vminuw", int_ppc_altivec_vminuw>;
-def VMRGHB : VX1_Int<12 , "vmrghb", int_ppc_altivec_vmrghb>;
-def VMRGHH : VX1_Int<76 , "vmrghh", int_ppc_altivec_vmrghh>;
-def VMRGHW : VX1_Int<140, "vmrghw", int_ppc_altivec_vmrghw>;
-def VMRGLB : VX1_Int<268, "vmrglb", int_ppc_altivec_vmrglb>;
-def VMRGLH : VX1_Int<332, "vmrglh", int_ppc_altivec_vmrglh>;
-def VMRGLW : VX1_Int<396, "vmrglw", int_ppc_altivec_vmrglw>;
+def VMRGHB : VXForm_1< 12, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmrghb $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
+ VRRC:$vB, VMRGHB_shuffle_mask))]>;
+def VMRGHH : VXForm_1< 76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmrghh $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
+ VRRC:$vB, VMRGHH_shuffle_mask))]>;
+def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmrghw $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
+ VRRC:$vB, VMRGHW_shuffle_mask))]>;
+def VMRGLB : VXForm_1<268, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmrglb $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
+ VRRC:$vB, VMRGLB_shuffle_mask))]>;
+def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmrglh $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
+ VRRC:$vB, VMRGLH_shuffle_mask))]>;
+def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+ "vmrglw $vD, $vA, $vB", VecFP,
+ [(set VRRC:$vD, (vector_shuffle (v16i8 VRRC:$vA),
+ VRRC:$vB, VMRGLW_shuffle_mask))]>;
def VMSUMMBM : VA1a_Int<37, "vmsummbm", int_ppc_altivec_vmsummbm>;
def VMSUMSHM : VA1a_Int<40, "vmsumshm", int_ppc_altivec_vmsumshm>;
Index: llvm/lib/Target/PowerPC/README_ALTIVEC.txt
diff -u llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.17
llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.18
--- llvm/lib/Target/PowerPC/README_ALTIVEC.txt:1.17 Thu Apr 6 14:19:38 2006
+++ llvm/lib/Target/PowerPC/README_ALTIVEC.txt Thu Apr 6 16:11:54 2006
@@ -129,6 +129,3 @@
//===----------------------------------------------------------------------===//
-Lower "merges" in the front-end to shuffles, reconstruct in the backend.
-
-//===----------------------------------------------------------------------===//
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