Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.125 -> 1.126
PPCISelLowering.h updated: 1.37 -> 1.38
---
Log message:
Inform the dag combiner that the predicate compares only return a low bit.
---
Diffs of the changes: (+39 -1)
PPCISelLowering.cpp | 35 ++++++++++++++++++++++++++++++++++-
PPCISelLowering.h | 5 +++++
2 files changed, 39 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.126
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.125 Sat Apr 1 18:43:36 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Sun Apr 2 00:26:07 2006
@@ -760,7 +760,7 @@
return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
}
case ISD::INTRINSIC_WO_CHAIN: {
- unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(0))->getValue();
+ unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
// If this is a lowered altivec predicate compare, CompareOpc is set to the
// opcode number of the comparison.
@@ -1409,6 +1409,39 @@
return SDOperand();
}
+void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t &KnownZero,
+ uint64_t &KnownOne,
+ unsigned Depth) const {
+ KnownZero = 0;
+ KnownOne = 0;
+ switch (Op.getOpcode()) {
+ default: break;
+ case ISD::INTRINSIC_WO_CHAIN: {
+ switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
+ default: break;
+ case Intrinsic::ppc_altivec_vcmpbfp_p:
+ case Intrinsic::ppc_altivec_vcmpeqfp_p:
+ case Intrinsic::ppc_altivec_vcmpequb_p:
+ case Intrinsic::ppc_altivec_vcmpequh_p:
+ case Intrinsic::ppc_altivec_vcmpequw_p:
+ case Intrinsic::ppc_altivec_vcmpgefp_p:
+ case Intrinsic::ppc_altivec_vcmpgtfp_p:
+ case Intrinsic::ppc_altivec_vcmpgtsb_p:
+ case Intrinsic::ppc_altivec_vcmpgtsh_p:
+ case Intrinsic::ppc_altivec_vcmpgtsw_p:
+ case Intrinsic::ppc_altivec_vcmpgtub_p:
+ case Intrinsic::ppc_altivec_vcmpgtuh_p:
+ case Intrinsic::ppc_altivec_vcmpgtuw_p:
+ KnownZero = ~1U; // All bits but the low one are known to be zero.
+ break;
+ }
+ }
+ }
+}
+
+
/// getConstraintType - Given a constraint letter, return the type of
/// constraint it is for this target.
PPCTargetLowering::ConstraintType
Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37
llvm/lib/Target/PowerPC/PPCISelLowering.h:1.38
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.37 Thu Mar 30 23:13:27 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h Sun Apr 2 00:26:07 2006
@@ -133,6 +133,11 @@
virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+ virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+ uint64_t Mask,
+ uint64_t &KnownZero,
+ uint64_t &KnownOne,
+ unsigned Depth = 0) const;
/// LowerArguments - This hook must be implemented to indicate how we
should
/// lower the arguments for the specified function, into the specified DAG.
virtual std::vector<SDOperand>
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