Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.213 -> 1.214
SelectionDAGISel.cpp updated: 1.103 -> 1.104
---
Log message:
Rather than attempting to legalize 1 x float, make sure the SD ISel never
generates it. Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.
The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.
---
Diffs of the changes: (+24 -48)
LegalizeDAG.cpp | 42 ------------------------------------------
SelectionDAGISel.cpp | 30 ++++++++++++++++++++++++------
2 files changed, 24 insertions(+), 48 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.213
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.214
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.213 Sun Nov 20 16:56:56 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Nov 21 19:29:36 2005
@@ -925,26 +925,6 @@
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
- case ISD::VLOAD:
- Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
-
- // If we just have one element, scalarize the result. Otherwise, check to
- // see if we support this operation on this type at this width. If not,
- // split the vector in half and try again.
- if (1 == cast<ConstantSDNode>(Node->getOperand(2))->getValue()) {
- MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
- Result = LegalizeOp(DAG.getLoad(SVT, Tmp1, Tmp2, Node->getOperand(4)));
- } else {
- assert(0 && "Expand case for vectors unimplemented");
- }
-
- // Since loads produce two values, make sure to remember that we legalized
- // both of them.
- AddLegalizedOperand(SDOperand(Node, 0), Result);
- AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
- return Result.getValue(Op.ResNo);
-
case ISD::EXTLOAD:
case ISD::SEXTLOAD:
case ISD::ZEXTLOAD: {
@@ -1685,28 +1665,6 @@
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
Tmp1,Tmp2);
break;
- // Vector binary operators
- case ISD::VADD:
- case ISD::VSUB:
- case ISD::VMUL: {
- Tmp1 = Node->getOperand(0); // Element Count
- Tmp2 = Node->getOperand(1); // Element Type
-
- // If we just have one element, scalarize the result. Otherwise, check to
- // see if we support this operation on this type at this width. If not,
- // split the vector in half and try again.
- if (1 == cast<ConstantSDNode>(Tmp1)->getValue()) {
- MVT::ValueType SVT = cast<VTSDNode>(Tmp2)->getVT();
-
- Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), SVT), SVT,
- LegalizeOp(Node->getOperand(2)),
- LegalizeOp(Node->getOperand(3)));
- } else {
- assert(0 && "Expand case for vectors unimplemented");
- }
- break;
- }
-
case ISD::BUILD_PAIR: {
MVT::ValueType PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.103
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.104
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.103 Sat Nov 19
12:40:42 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Nov 21 19:29:36 2005
@@ -517,9 +517,19 @@
setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
} else {
const PackedType *PTy = cast<PackedType>(Ty);
- SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
- SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
- setValue(&I, DAG.getNode(VecOp, Op1.getValueType(), Num, Typ, Op1, Op2));
+ unsigned NumElements = PTy->getNumElements();
+ MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
+
+ // Immediately scalarize packed types containing only one element, so that
+ // the Legalize pass does not have to deal with them.
+ if (NumElements == 1) {
+ unsigned Opc = MVT::isFloatingPoint(PVT) ? FPOp : IntOp;
+ setValue(&I, DAG.getNode(Opc, PVT, Op1, Op2));
+ } else {
+ SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
+ SDOperand Typ = DAG.getValueType(PVT);
+ setValue(&I, DAG.getNode(VecOp, Op1.getValueType(), Num, Typ, Op1, Op2));
+ }
}
}
@@ -726,9 +736,17 @@
if (Type::PackedTyID == Ty->getTypeID()) {
const PackedType *PTy = cast<PackedType>(Ty);
- L = DAG.getVecLoad(PTy->getNumElements(),
- TLI.getValueType(PTy->getElementType()), Root, Ptr,
- DAG.getSrcValue(I.getOperand(0)));
+ unsigned NumElements = PTy->getNumElements();
+ MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
+
+ // Immediately scalarize packed types containing only one element, so that
+ // the Legalize pass does not have to deal with them.
+ if (NumElements == 1) {
+ L = DAG.getLoad(PVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0)));
+ } else {
+ L = DAG.getVecLoad(NumElements, PVT, Root, Ptr,
+ DAG.getSrcValue(I.getOperand(0)));
+ }
} else {
L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr,
DAG.getSrcValue(I.getOperand(0)));
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