Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.262 -> 1.263
SelectionDAGISel.cpp updated: 1.123 -> 1.124
---
Log message:
bswap implementation
---
Diffs of the changes: (+83 -0)
LegalizeDAG.cpp | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++
SelectionDAGISel.cpp | 15 +++++++++++
2 files changed, 83 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.262
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.263
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.262 Fri Jan 13 11:48:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Fri Jan 13 21:14:10 2006
@@ -2217,6 +2217,58 @@
}
break;
+ case ISD::BSWAP:
+ Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
+ switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
+ case TargetLowering::Legal:
+ if (Tmp1 != Node->getOperand(0))
+ Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
+ break;
+ case TargetLowering::Promote: {
+ MVT::ValueType OVT = Tmp1.getValueType();
+ MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
+
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
+ Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
+ Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
+ DAG.getConstant(DiffBits,
TLI.getShiftAmountTy()));
+ break;
+ }
+ case TargetLowering::Custom:
+ assert(0 && "Cannot custom legalize this yet!");
+ case TargetLowering::Expand: {
+ MVT::ValueType VT = Tmp1.getValueType();
+ switch (VT) {
+ default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
+ case MVT::i16:
+ Tmp2 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(8, TLI.getShiftAmountTy()));
+ Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(8, TLI.getShiftAmountTy()));
+ Result = DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
+ break;
+ case MVT::i32:
+ Tmp4 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(24, TLI.getShiftAmountTy()));
+ Tmp3 = DAG.getNode(ISD::SHL, VT, Tmp1,
+ DAG.getConstant(8, TLI.getShiftAmountTy()));
+ Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(8, TLI.getShiftAmountTy()));
+ Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1,
+ DAG.getConstant(24, TLI.getShiftAmountTy()));
+ Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000,
VT));
+ Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
+ Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
+ Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
+ Result = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
+ break;
+ }
+ break;
+ }
+ }
+ break;
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
@@ -3027,6 +3079,14 @@
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
break;
}
+ case ISD::BSWAP:
+ Tmp1 = Node->getOperand(0);
+ Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
+ Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
+ Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
+ DAG.getConstant(getSizeInBits(NVT) -
getSizeInBits(VT),
+ TLI.getShiftAmountTy()));
+ break;
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
@@ -3636,6 +3696,14 @@
Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
break;
+ case ISD::BSWAP: {
+ ExpandOp(Node->getOperand(0), Lo, Hi);
+ SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
+ Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
+ Lo = TempLo;
+ break;
+ }
+
case ISD::CTPOP:
ExpandOp(Node->getOperand(0), Lo, Hi);
Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.123
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.124
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.123 Thu Jan 12
20:50:02 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Fri Jan 13 21:14:10 2006
@@ -989,6 +989,21 @@
DAG.setRoot(Tmp.getValue(1));
return 0;
}
+ case Intrinsic::bswap_i16:
+ setValue(&I, DAG.getNode(ISD::BSWAP,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
+ case Intrinsic::bswap_i32:
+ setValue(&I, DAG.getNode(ISD::BSWAP,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
+ case Intrinsic::bswap_i64:
+ setValue(&I, DAG.getNode(ISD::BSWAP,
+ getValue(I.getOperand(1)).getValueType(),
+ getValue(I.getOperand(1))));
+ return 0;
case Intrinsic::cttz:
setValue(&I, DAG.getNode(ISD::CTTZ,
getValue(I.getOperand(1)).getValueType(),
_______________________________________________
llvm-commits mailing list
llvm-commits@cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
