[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAGISel.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.309 -> 1.310
SelectionDAGISel.cpp updated: 1.177 -> 1.178
---
Log message:

Add more vector NodeTypes: VSDIV, VUDIV, VAND, VOR, and VXOR.


---
Diffs of the changes:  (+20 -8)

 LegalizeDAG.cpp      |   18 ++++++++++++++----
 SelectionDAGISel.cpp |   10 ++++++----
 2 files changed, 20 insertions(+), 8 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.309 
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.310
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.309 Thu Mar  2 18:19:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp       Fri Mar  3 01:01:07 2006
@@ -152,9 +152,14 @@
 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
   switch (VecOp) {
   default: assert(0 && "Don't know how to scalarize this opcode!");
-  case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
-  case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
-  case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
+  case ISD::VADD:  return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
+  case ISD::VSUB:  return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
+  case ISD::VMUL:  return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
+  case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
+  case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
+  case ISD::VAND:  return MVT::isInteger(VT) ? ISD::AND : 0;
+  case ISD::VOR:   return MVT::isInteger(VT) ? ISD::OR  : 0;
+  case ISD::VXOR:  return MVT::isInteger(VT) ? ISD::XOR : 0;
   }
 }
 
@@ -3646,7 +3651,12 @@
   }
   case ISD::VADD:
   case ISD::VSUB:
-  case ISD::VMUL: {
+  case ISD::VMUL:
+  case ISD::VSDIV:
+  case ISD::VUDIV:
+  case ISD::VAND:
+  case ISD::VOR:
+  case ISD::VXOR: {
     unsigned NumElements 
=cast<ConstantSDNode>(Node->getOperand(0))->getValue();
     MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
     MVT::ValueType TVT = (NumElements/2 > 1)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.177 
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.178
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.177    Thu Mar  2 
18:19:44 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp  Fri Mar  3 01:01:07 2006
@@ -496,15 +496,17 @@
   }
   void visitDiv(User &I) {
     const Type *Ty = I.getType();
-    visitBinary(I, Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV, 0);
+    visitBinary(I,
+                Ty->isSigned() ? ISD::SDIV : ISD::UDIV, ISD::FDIV,
+                Ty->isSigned() ? ISD::VSDIV : ISD::VUDIV);
   }
   void visitRem(User &I) {
     const Type *Ty = I.getType();
     visitBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, ISD::FREM, 0);
   }
-  void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, 0); }
-  void visitOr (User &I) { visitBinary(I, ISD::OR,  0, 0); }
-  void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, 0); }
+  void visitAnd(User &I) { visitBinary(I, ISD::AND, 0, ISD::VAND); }
+  void visitOr (User &I) { visitBinary(I, ISD::OR,  0, ISD::VOR); }
+  void visitXor(User &I) { visitBinary(I, ISD::XOR, 0, ISD::VXOR); }
   void visitShl(User &I) { visitShift(I, ISD::SHL); }
   void visitShr(User &I) { 
     visitShift(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);



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