dlav-sc wrote: > A quick look at the RISCV ISA and it says that the JAL instruction is pc > relative and can jump +/- 1MB. JALR gets the upper 20 bits from a general > purpose register and it includes 12 low bits in its instruction encoding. I > know almost nothing about rv32, but is this what you mean by a Large Memory > Model, the use of the JALR instruction? I didn't find the part that talks > about how JALR works in rv64, but it seems likely it can specify an arbitrary > 64-bit address?
> I know almost nothing about rv32, but is this what you mean by a Large Memory > Model, the use of the JALR instruction? yep. https://github.com/llvm/llvm-project/pull/99336 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
