dlav-sc wrote: > A quick look at the RISCV ISA and it says that the JAL instruction is pc > relative and can jump +/- 1MB. JALR gets the upper 20 bits from a general > purpose register and it includes 12 low bits in its instruction encoding. I > know almost nothing about rv32, but is this what you mean by a Large Memory > Model, the use of the JALR instruction? I didn't find the part that talks > about how JALR works in rv64, but it seems likely it can specify an arbitrary > 64-bit address?
>I didn't find the part that talks about how JALR works in rv64, but it seems >likely it can specify an arbitrary 64-bit address? Nope, you can't specify an arbitrary 64-bit address in RISCV now. Here https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/388#issuecomment-1737115297 they write that if Large Code Model is approved then at least 6 instructions well be need to do it: ``` lui t0, <highest20> addi t0, t0, <higher12> slli t0, 32 auipc t1, <hi20> addi t1, t1, t0 ld t1, <lo12>(t1) ``` https://github.com/llvm/llvm-project/pull/99336 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
