On Thu, Feb 06, 2014 at 06:37:27PM +0100, Torsten Duwe wrote: > On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote: > > On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote: > > > x86 has them, MIPS has them, ARM has them, even ia64 has them: > > > ticket locks. They reduce memory bus and cache pressure especially > > > for contended spinlocks, increasing performance. > > > > > > This patch is a port of the x86 spin locks, mostly written in C, > > > to the powerpc, introducing inline asm where needed. The pSeries > > > directed yield for vCPUs is taken care of by an additional "holder" > > > field in the lock. > > > > > > > A few questions; what's with the ppc64 holder thing? Not having a 32bit > > spinlock_t is sad. > > I must admit that I haven't tested the patch on non-pseries ppc64 nor on > ppc32. Only ppc64 has the ldarx and I tried to atomically replace the > holder along with the locks. That might prove unneccessary.
But what is the holder for? Can't we do away with that field? > > Can you pair lwarx with sthcx ? I couldn't immediately find the answer > > in the PowerISA doc. If so I think you can do better by being able to > > atomically load both tickets but only storing the head without affecting > > the tail. > > V2.06b, Book II, Chapter 3, "sthcx" says: > | If a reservation exists and the length associated [...] is not 2 bytes, > | it is undefined whether (RS)_48:63 are stored [...] > > That doesn't make me feel comfortable :( That's on page 692, right? The way I read that is of the lharx/sthcx don't have the exact same address, storage is undefined. But I can't find mention of non-matching load and store size, although I can imagine it being the same undefined. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
