On Thu, Feb 06, 2014 at 11:37:37AM +0100, Torsten Duwe wrote: > x86 has them, MIPS has them, ARM has them, even ia64 has them: > ticket locks. They reduce memory bus and cache pressure especially > for contended spinlocks, increasing performance. > > This patch is a port of the x86 spin locks, mostly written in C, > to the powerpc, introducing inline asm where needed. The pSeries > directed yield for vCPUs is taken care of by an additional "holder" > field in the lock. >
A few questions; what's with the ppc64 holder thing? Not having a 32bit spinlock_t is sad. Can you pair lwarx with sthcx ? I couldn't immediately find the answer in the PowerISA doc. If so I think you can do better by being able to atomically load both tickets but only storing the head without affecting the tail. In that case you can avoid the ll/sc on unlock, because only the lock owner can modify the tail, so you can use a single half-word store. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
