On Fri, Jul 15, 2011 at 11:40:27AM -0500, Ayman Elkhashab wrote: > @@ -1582,8 +1628,8 @@ static int __init ppc4xx_setup_one_pciex_POM(struct > ppc4xx_pciex_port *port, > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); > dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); > dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); > - /* Note that 3 here means enabled | single region */ > - dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3); > + dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, > + sa | DCRO_PEGPL_OMRxMSKL_VAL);
Didn't you just change "sa | 3" to "sa | 1" ? <snip> > index 56d9e5d..61b3659 100644 > --- a/arch/powerpc/sysdev/ppc4xx_pci.h > +++ b/arch/powerpc/sysdev/ppc4xx_pci.h > @@ -464,6 +464,18 @@ > #define PECFG_POM2LAL 0x390 > #define PECFG_POM2LAH 0x394 > > +/* 460sx only */ > +#define PECFG_460SX_DLLSTA 0x3f8 > + > +/* 460sx Bit Mappings */ > +#define PECFG_460SX_DLLSTA_LINKUP 0x00000010 > +#define DCRO_PEGPL_460SX_OMR1MSKL_UOT 0x00000004 > + > +/* PEGPL Bit Mappings */ > +#define DCRO_PEGPL_OMRxMSKL_VAL 0x00000001 > +#define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002 > +#define DCRO_PEGPL_OMR3MSKL_IO 0x00000002 > + > /* SDR Bit Mappings */ > #define PESDRx_RCSSET_HLDPLB 0x10000000 > #define PESDRx_RCSSET_RSTGU 0x01000000 Yours Tony _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
