> The PPC440X currently uses 256M TLB entries to pin the
> lowmem. When we go for a relocatable kernel we have to :
>
> 1) Restrict the kernel load address to be 256M aligned
>
> OR
>
> 2) Use 16M TLB(the next possible TLB page size supported)
> entries till the first
> 256M and then use the 256M TLB entries for the rest of lowmem.
What is wrong with:
3) Use 256M TLB entries with the lowest one including
addresses below the kernel base.
Clearly the kernel shouldn't be accessing the addresses
below its base address - but that is true of a lot of
address space mapped into the kernel.
David
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