Sure, the memory controllers don't do coherency. I'm slightly
worried
about two things:
1) Will the generic code use M=0 as well? Is it a problem if it
doesn't?
We can make it not do it.
2) Do lwarx. etc. work in M=0?
They should hopefully... as long as you don't rely on the reservation
blowing as a result of a DMA write.
Hmm, this really depends on whether the DMA transfers generate bus
cycles
that require coherency or not.
They do not; device DMA never goes to the 6xx bus with this bridge.
Not the other way around. M=1 only forces
bus cycles to be snooped by other processors (asserting the GBL signal
on 603/604/750 busses).
Right, it enables sending probes, not receiving them. On this CPU
anyway.
The architecture specification is quite silent on this all.
Segher
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
