On Mon, 2008-12-15 at 10:25 -0800, Trent Piepho wrote: > The MTD system supports operation where a direct mapped flash chip is > mapped twice. The normal mapping is a standard ioremap(), which is > non-cached and guarded on powerpc. The second mapping is used only for > reads and can be cached and non-guarded. Currently, only the pxa2xx > mapping driver makes use of this feature. This patch adds support to the > physmap_of driver on PPC32 platforms for this cached mapping mode.
This can be dangerous tho. I think it's illegal as per the architecture to have the same physical address mapped twice with different caching attributes. More specifically, various processors can get very upset if you do an uncached access that happens to hit a line in the cache. The problem gets worsened by the fact that cores that support speculative loads and prefetch will potentially bring anything mapped into the cache even if it's not directly accessed. So you have to be very careful and first verify that on whatever core you intend to use that feature, what you are doing is indeed safe. Cheers, Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
