On 08/03/2022, 14:50:38, Nicholas Piggin wrote: > mtmsrd L=1 can clear MSR[RI] without the previous MSR value; it does > not require sync; it can be moved later to before SRRs are live. > > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
Reviewed-by: Laurent Dufour <lduf...@linux.ibm.com> > --- > arch/powerpc/kernel/rtas_entry.S | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/powerpc/kernel/rtas_entry.S > b/arch/powerpc/kernel/rtas_entry.S > index 45fa661c2ff6..7b93687b9a10 100644 > --- a/arch/powerpc/kernel/rtas_entry.S > +++ b/arch/powerpc/kernel/rtas_entry.S > @@ -109,13 +109,13 @@ _GLOBAL(enter_rtas) > andc r6,r0,r9 > > __enter_rtas: > - sync /* disable RI so SRR0/1 */ > - mtmsrd r0 /* don't get trashed */ > - > LOAD_REG_ADDR(r4, rtas) > ld r5,RTASENTRY(r4) /* get the rtas->entry value */ > ld r4,RTASBASE(r4) /* get the rtas->base value */ > > + li r0,0 > + mtmsrd r0,1 /* disable RI before using SRR0/1 */ > + > mtspr SPRN_SRR0,r5 > mtspr SPRN_SRR1,r6 > RFI_TO_KERNEL
