Binding document adding for Freescale MSI support.
Signed-off-by: Jason Jin <[EMAIL PROTECTED]>
---
Updated to V2 version per Segher's suggestion.
Documentation/powerpc/booting-without-of.txt | 40 +++++++++++++++++++++++++-
1 files changed, 39 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt
b/Documentation/powerpc/booting-without-of.txt
index 1d2a772..887783c 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -57,7 +57,10 @@ Table of Contents
n) 4xx/Axon EMAC ethernet nodes
o) Xilinx IP cores
p) Freescale Synchronous Serial Interface
- q) USB EHCI controllers
+ q) USB EHCI controllers
+ r) Freescale Display Interface Unit
+ s) Freescale on board FPGA
+ t) Freescael MSI interrupt controller
VII - Marvell Discovery mv64[345]6x System Controller chips
1) The /system-controller node
@@ -2870,6 +2873,41 @@ platforms are moved over to use the
flattened-device-tree model.
reg = <0xe8000000 32>;
};
+ t) Freescale MSI interrupt controller
+
+ Reguired properities:
+ - compatible : set as "fsl,86xx-MSI" for 86xx cpu, "fsl,85xx-MSI" for 85xx
+ cpu and "fsl,83xx-MSI" for 83xx cpu.
+ - reg : should contain the address and the length of the shared message
+ interrupt register set.
+ - msi-available-ranges: use <start count> style section to define which
+ msi interrupt can be used in the 256 msi interrupts.
+ - interrupts : each one of the interrupts here is one entry per 32 MSIs,
+ and routed to the host interrupt controller. the interrupts should
+ be set as edge sensitive.
+ - interrupt-parent: the phandle for the interrupt controller
+ that services interrupts for this device. for 83xx cpu, the interrupts
+ are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
+ to MPIC.
+
+ Example (86xx CPU)
+ [EMAIL PROTECTED] {
+ compatible = "fsl,86xx-MSI";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xb0 0
+ 0xb1 0
+ 0xb2 0
+ 0xb3 0
+ 0xb4 0
+ 0xb5 0
+ 0xb6 0
+ 0xb7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+
VII - Marvell Discovery mv64[345]6x System Controller chips
===========================================================
--
1.5.4
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