On Thu, 2008-05-08 at 00:17 -0700, Nick Spence wrote: > The page protection seemed to be allocated on a per pte basis, where > each PTE is a small fixed size. I will need to check the TLB setup > further.
The problem is that it will then be part of the linear mapping, which means you'll end up with a double cacheable & non-cacheable mapping for that memory, this is not nice ... it might work as long as we stick to having G bit set for the whole linear mapping but it's going to come back and bite. I still think you should look closely whether it could be carved out of the end of memory... even if that involves changing application code. Now, if you aren't afraid of cache paradox caused by the linear mapping, then carve it out of the LMB wherever it is rather than lmb_reserve() it. That would probably work. Ben. _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
