Add device tree source file for CM5200 board.
Signed-off-by: Marian Balakowicz <[EMAIL PROTECTED]>
---
arch/powerpc/boot/dts/cm5200.dts | 236 ++++++++++++++++++++++++++++++++++++++
1 files changed, 236 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/cm5200.dts
diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
new file mode 100644
index 0000000..74e82bf
--- /dev/null
+++ b/arch/powerpc/boot/dts/cm5200.dts
@@ -0,0 +1,236 @@
+/*
+ * CM5200 board Device Tree Source
+ *
+ * Copyright (C) 2007 Semihalf
+ * Marian Balakowicz <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/*
+ * WARNING: Do not depend on this tree layout remaining static just yet.
+ * The MPC5200 device tree conventions are still in flux
+ * Keep an eye on the linuxppc-dev mailing list for more details
+ */
+
+/ {
+ model = "schindler,cm5200";
+ compatible = "schindler,cm5200","mpc5200-simple-platform";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>;
+ i-cache-line-size = <20>;
+ d-cache-size = <4000>; // L1, 16K
+ i-cache-size = <4000>; // L1, 16K
+ timebase-frequency = <0>; // from bootloader
+ bus-frequency = <0>; // from bootloader
+ clock-frequency = <0>; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <00000000 04000000>; // 64MB
+ };
+
+ [EMAIL PROTECTED] {
+ model = "fsl,mpc5200b";
+ compatible = "fsl,mpc5200b";
+ revision = ""; // from bootloader
+ device_type = "soc";
+ ranges = <0 f0000000 0000c000>;
+ reg = <f0000000 00000100>;
+ bus-frequency = <0>; // from bootloader
+ system-frequency = <0>; // from bootloader
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-cdm","mpc5200-cdm";
+ reg = <200 38>;
+ };
+
+ mpc5200_pic: [EMAIL PROTECTED] {
+ // 5200 interrupts are encoded into two levels;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ compatible = "mpc5200b-pic","mpc5200-pic";
+ reg = <500 80>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <600 10>;
+ interrupts = <1 9 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ fsl,has-wdt;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <610 10>;
+ interrupts = <1 a 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <620 10>;
+ interrupts = <1 b 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <630 10>;
+ interrupts = <1 c 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <640 10>;
+ interrupts = <1 d 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <650 10>;
+ interrupts = <1 e 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <660 10>;
+ interrupts = <1 f 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // General Purpose Timer
+ compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
+ reg = <670 10>;
+ interrupts = <1 10 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // Real time clock
+ compatible = "mpc5200b-rtc","mpc5200-rtc";
+ reg = <800 100>;
+ interrupts = <1 5 0 1 6 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-gpio","mpc5200-gpio";
+ reg = <b00 40>;
+ interrupts = <1 7 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
+ reg = <c00 40>;
+ interrupts = <1 8 0 0 3 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-spi","mpc5200-spi";
+ reg = <f00 20>;
+ interrupts = <2 d 0 2 e 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ device_type = "usb-ohci-be";
+ compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
+ reg = <1000 ff>;
+ interrupts = <2 6 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
+ reg = <1200 80>;
+ interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
+ 3 4 0 3 5 0 3 6 0 3 7 0
+ 3 8 0 3 9 0 3 a 0 3 b 0
+ 3 c 0 3 d 0 3 e 0 3 f 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-xlb","mpc5200-xlb";
+ reg = <1f00 100>;
+ };
+
+ [EMAIL PROTECTED] { // PSC1
+ device_type = "serial";
+ compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
+ port-number = <0>; // Logical port assignment
+ reg = <2000 100>;
+ interrupts = <2 1 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // PSC2
+ device_type = "serial";
+ compatible = "mpc5200-psc-uart";
+ port-number = <1>; // Logical port assignment
+ reg = <2200 100>;
+ interrupts = <2 2 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // PSC3
+ device_type = "serial";
+ compatible = "mpc5200-psc-uart";
+ port-number = <2>; // Logical port assignment
+ reg = <2400 100>;
+ interrupts = <2 3 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] { // PSC6
+ device_type = "serial";
+ compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
+ port-number = <5>; // Logical port assignment
+ reg = <2c00 100>;
+ interrupts = <2 4 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ device_type = "network";
+ compatible = "mpc5200b-fec","mpc5200-fec";
+ reg = <3000 800>;
+ local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in
by U-Boot */
+ interrupts = <2 5 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
+ reg = <3d40 40>;
+ interrupts = <2 10 0>;
+ interrupt-parent = <&mpc5200_pic>;
+ fsl5200-clocking;
+ };
+
+ [EMAIL PROTECTED] {
+ compatible = "mpc5200b-sram","mpc5200-sram";
+ reg = <8000 4000>;
+ };
+ };
+};
_______________________________________________
Linuxppc-dev mailing list
[email protected]
https://ozlabs.org/mailman/listinfo/linuxppc-dev
