From: Frank Li <[email protected]> Commercial users and hardware vendors migrated to Zephyr or other RTOS solutions years ago, leaving the NOMMU platform support effectively unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the i.MX platform code. Signed-off-by: Frank Li <[email protected]> --- drivers/clk/imx/Kconfig | 6 - drivers/clk/imx/Makefile | 1 - drivers/clk/imx/clk-imxrt1050.c | 182 ---------------------------- include/dt-bindings/clock/imxrt1050-clock.h | 72 ----------- 4 files changed, 261 deletions(-) diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig index b292e7ca5c248..92ae6e095fadb 100644 --- a/drivers/clk/imx/Kconfig +++ b/drivers/clk/imx/Kconfig @@ -123,9 +123,3 @@ config CLK_IMX95_BLK_CTL help Build the clock driver for i.MX95 BLK CTL -config CLK_IMXRT1050 - tristate "IMXRT1050 CCM Clock Driver" - depends on SOC_IMXRT || COMPILE_TEST - select MXC_CLK - help - Build the driver for i.MXRT1050 CCM Clock Driver diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 208b46873a18c..e71a6a8f8b04f 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -56,5 +56,4 @@ obj-$(CONFIG_CLK_IMX6SX) += clk-imx6sx.o obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o -obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o obj-$(CONFIG_CLK_VF610) += clk-vf610.o diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c deleted file mode 100644 index efd1ac9d8eeb7..0000000000000 --- a/drivers/clk/imx/clk-imxrt1050.c +++ /dev/null @@ -1,182 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * Copyright (C) 2021 - * Author(s): - * Jesse Taube <[email protected]> - * Giulio Benetti <[email protected]> - */ -#include <linux/clk.h> -#include <linux/of_address.h> -#include <linux/of_irq.h> -#include <linux/platform_device.h> -#include <dt-bindings/clock/imxrt1050-clock.h> - -#include "clk.h" - -static const char * const pll_ref_sels[] = {"osc", "dummy", }; -static const char * const per_sels[] = {"ipg_pdof", "osc", }; -static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", }; -static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", }; -static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", }; -static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", }; -static const char *const pre_periph_sels[] = { - "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", }; -static const char *const periph_sels[] = { "pre_periph_sel", "todo", }; -static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *const lpuart_sels[] = { "pll3_80m", "osc", }; -static const char *const lcdif_sels[] = { - "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m", - "pll2_pfd1_594m", "pll3_pfd1_664_62m", }; -static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", }; -static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", }; - -static struct clk_hw **hws; -static struct clk_hw_onecell_data *clk_hw_data; - -static int imxrt1050_clocks_probe(struct platform_device *pdev) -{ - void __iomem *ccm_base; - void __iomem *pll_base; - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - struct device_node *anp; - int ret; - - clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, - IMXRT1050_CLK_END), GFP_KERNEL); - if (WARN_ON(!clk_hw_data)) - return -ENOMEM; - - clk_hw_data->num = IMXRT1050_CLK_END; - hws = clk_hw_data->hws; - - hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc"); - - anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop"); - pll_base = devm_of_iomap(dev, anp, 0, NULL); - of_node_put(anp); - if (WARN_ON(IS_ERR(pll_base))) { - ret = PTR_ERR(pll_base); - goto unregister_hws; - } - - /* Anatop clocks */ - hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL); - - hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel", - pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel", - pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel", - pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel", - pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); - - hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm", - "pll1_arm_ref_sel", pll_base + 0x0, 0x7f); - hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", - "pll2_sys_ref_sel", pll_base + 0x30, 0x1); - hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", - "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1); - hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5_video", - "pll5_video_ref_sel", pll_base + 0xa0, 0x7f); - - /* PLL bypass out */ - hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", pll_base + 0x0, 16, 1, - pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", pll_base + 0x30, 16, 1, - pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", pll_base + 0x10, 16, 1, - pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); - hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", pll_base + 0xa0, 16, 1, - pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); - - hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel", - "pll5_video", pll_base + 0xa0, 19, 2); - hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div", - "video_post_div_sel", pll_base + 0x170, 30, 2); - - hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); - - hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_sys", pll_base + 0x100, 0); - hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_sys", pll_base + 0x100, 1); - hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_sys", pll_base + 0x100, 2); - hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", pll_base + 0xf0, 1); - hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", pll_base + 0xf0, 3); - - /* CCM clocks */ - ccm_base = devm_platform_ioremap_resource(pdev, 0); - if (WARN_ON(IS_ERR(ccm_base))) { - ret = PTR_ERR(ccm_base); - goto unregister_hws; - } - - hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3); - hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2, - pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); - hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1, - periph_sels, ARRAY_SIZE(periph_sels)); - hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels)); - hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels)); - hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1, - lpuart_sels, ARRAY_SIZE(lpuart_sels)); - hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3, - lcdif_sels, ARRAY_SIZE(lcdif_sels)); - hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1, - per_sels, ARRAY_SIZE(per_sels)); - hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1, - semc_alt_sels, ARRAY_SIZE(semc_alt_sels)); - hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1, - semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL); - - hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3); - hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2); - hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per", "per_sel", ccm_base + 0x1C, 0, 5); - - hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", ccm_base + 0x24, 11, 3); - hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", ccm_base + 0x24, 16, 3); - hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf", "lpuart_sel", ccm_base + 0x24, 0, 6); - hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_sel", ccm_base + 0x38, 12, 3); - hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", ccm_base + 0x18, 23, 3); - - hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); - hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); - hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); - hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28); - hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif", ccm_base + 0x74, 10); - hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6); - hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); - imx_check_clk_hws(hws, IMXRT1050_CLK_END); - - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); - if (ret < 0) { - dev_err(dev, "Failed to register clks for i.MXRT1050.\n"); - goto unregister_hws; - } - return 0; - -unregister_hws: - imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END); - return ret; -} -static const struct of_device_id imxrt1050_clk_of_match[] = { - { .compatible = "fsl,imxrt1050-ccm" }, - { /* Sentinel */ } -}; -MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match); - -static struct platform_driver imxrt1050_clk_driver = { - .probe = imxrt1050_clocks_probe, - .driver = { - .name = "imxrt1050-ccm", - .of_match_table = imxrt1050_clk_of_match, - }, -}; -module_platform_driver(imxrt1050_clk_driver); - -MODULE_DESCRIPTION("NXP i.MX RT1050 clock driver"); -MODULE_LICENSE("Dual BSD/GPL"); -MODULE_AUTHOR("Jesse Taube <[email protected]>"); -MODULE_AUTHOR("Giulio Benetti <[email protected]>"); diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h deleted file mode 100644 index 93bef0832d16d..0000000000000 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright(C) 2019 - * Author(s): Giulio Benetti <[email protected]> - */ - -#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H -#define __DT_BINDINGS_CLOCK_IMXRT1050_H - -#define IMXRT1050_CLK_DUMMY 0 -#define IMXRT1050_CLK_CKIL 1 -#define IMXRT1050_CLK_CKIH 2 -#define IMXRT1050_CLK_OSC 3 -#define IMXRT1050_CLK_PLL2_PFD0_352M 4 -#define IMXRT1050_CLK_PLL2_PFD1_594M 5 -#define IMXRT1050_CLK_PLL2_PFD2_396M 6 -#define IMXRT1050_CLK_PLL3_PFD0_720M 7 -#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8 -#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9 -#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10 -#define IMXRT1050_CLK_PLL2_198M 11 -#define IMXRT1050_CLK_PLL3_120M 12 -#define IMXRT1050_CLK_PLL3_80M 13 -#define IMXRT1050_CLK_PLL3_60M 14 -#define IMXRT1050_CLK_PLL1_BYPASS 15 -#define IMXRT1050_CLK_PLL2_BYPASS 16 -#define IMXRT1050_CLK_PLL3_BYPASS 17 -#define IMXRT1050_CLK_PLL5_BYPASS 19 -#define IMXRT1050_CLK_PLL1_REF_SEL 20 -#define IMXRT1050_CLK_PLL2_REF_SEL 21 -#define IMXRT1050_CLK_PLL3_REF_SEL 22 -#define IMXRT1050_CLK_PLL5_REF_SEL 23 -#define IMXRT1050_CLK_PRE_PERIPH_SEL 24 -#define IMXRT1050_CLK_PERIPH_SEL 25 -#define IMXRT1050_CLK_SEMC_ALT_SEL 26 -#define IMXRT1050_CLK_SEMC_SEL 27 -#define IMXRT1050_CLK_USDHC1_SEL 28 -#define IMXRT1050_CLK_USDHC2_SEL 29 -#define IMXRT1050_CLK_LPUART_SEL 30 -#define IMXRT1050_CLK_LCDIF_SEL 31 -#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32 -#define IMXRT1050_CLK_VIDEO_DIV 33 -#define IMXRT1050_CLK_ARM_PODF 34 -#define IMXRT1050_CLK_LPUART_PODF 35 -#define IMXRT1050_CLK_USDHC1_PODF 36 -#define IMXRT1050_CLK_USDHC2_PODF 37 -#define IMXRT1050_CLK_SEMC_PODF 38 -#define IMXRT1050_CLK_AHB_PODF 39 -#define IMXRT1050_CLK_LCDIF_PRED 40 -#define IMXRT1050_CLK_LCDIF_PODF 41 -#define IMXRT1050_CLK_USDHC1 42 -#define IMXRT1050_CLK_USDHC2 43 -#define IMXRT1050_CLK_LPUART1 44 -#define IMXRT1050_CLK_SEMC 45 -#define IMXRT1050_CLK_LCDIF_APB 46 -#define IMXRT1050_CLK_PLL1_ARM 47 -#define IMXRT1050_CLK_PLL2_SYS 48 -#define IMXRT1050_CLK_PLL3_USB_OTG 49 -#define IMXRT1050_CLK_PLL4_AUDIO 50 -#define IMXRT1050_CLK_PLL5_VIDEO 51 -#define IMXRT1050_CLK_PLL6_ENET 52 -#define IMXRT1050_CLK_PLL7_USB_HOST 53 -#define IMXRT1050_CLK_LCDIF_PIX 54 -#define IMXRT1050_CLK_USBOH3 55 -#define IMXRT1050_CLK_IPG_PDOF 56 -#define IMXRT1050_CLK_PER_CLK_SEL 57 -#define IMXRT1050_CLK_PER_PDOF 58 -#define IMXRT1050_CLK_DMA 59 -#define IMXRT1050_CLK_DMA_MUX 60 -#define IMXRT1050_CLK_END 61 - -#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ -- 2.43.0
