[PATCH 01/15] ARM: dts: qcom: sdx55: Add support for A7 PLL clock

[Manivannan Sadhasivam]

On SDX55 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasi...@linaro.org>
---
 arch/arm/boot/dts/qcom-sdx55.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi 
b/arch/arm/boot/dts/qcom-sdx55.dtsi
index e4180bbc4655..41c90f598359 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -352,6 +352,14 @@ intc: interrupt-controller@17800000 {
                              <0x17802000 0x1000>;
                };
 
+               a7pll: clock@17808000 {
+                       compatible = "qcom,sdx55-a7pll";
+                       reg = <0x17808000 0x1000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "bi_tcxo";
+                       #clock-cells = <0>;
+               };
+
                watchdog@17817000 {
                        compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
                        reg = <0x17817000 0x1000>;
-- 
2.25.1