On Tue, Feb 2, 2021 at 1:45 PM Bartosz Golaszewski <bgolaszew...@baylibre.com> wrote: > On Thu, Jan 28, 2021 at 4:36 PM Alban Bedel <alban.be...@aerq.com> wrote: > > > > From a quick glance at various datasheet the PCAL6524 seems to be the
Oh, even more typos datasheets > > only chip in this familly that support setting the drive mode of supports > > single pins. Other chips either don't support it at all, or can only > > set the drive mode of whole banks, which doesn't map to the GPIO API. > > > > Add a new flag, PCAL6524, to mark chips that have the extra registers > > needed for this feature. Then mark the needed register banks as > > readable and writable, here we don't set OUT_CONF as writable, > > although it is, as we only need to read it. Finally add a function > > that configure the OUT_INDCONF register when the GPIO API set the > > drive mode of the pins. ... > Maybe call it PCAL6524_TYPE for consistency with the ones below? In case you continue modifying this driver, I agree with Bart on PCAL6524_TYPE along with new OF_6524() macro. -- With Best Regards, Andy Shevchenko
