From: Sven Van Asbroeck <thesve...@gmail.com> Sent: Wednesday, July 1, 2020
9:52 PM
> Andy, Fabio,
>
> Does the following describe the mainline situation?
> Please correct if not.
>
> 1. imx6 ethernet ref_clk can be generated internally (by imx6) or
> externally (by PHY or oscillator on PCB) 2. if internal, fec's "ptp" clock
> in
> devicetree should be
> <&clks IMX6QDL_CLK_ENET_REF>
> 3. if external, fec's "ptp" clock should be that external clock,
> see 810c0ca879098 ("ARM: imx6q: support ptp and rmii clock from pad")
> 4. sabresd devicetree describes "ptp" clock as IMX6QDL_CLK_ENET_REF,
> although it's externally supplied (by PHY). This is incorrect.
No, ptp_clk is the same as enet_ref, it means ptp clock source from internal
pll.
So, for current upstream status for imx6q/6dl/6qp, ptp clock is from internal
pll,
rgmii gtx clock is from phy.
For 6qp, soc already support to route internal pll to rgmii gtx by setting
gpr5[9],
the patch force to use internal pll instead of external clk from phy. It doesn't
break imx6q/6dl. But as Fabio's said, it break old 6qp sabresd dtb.
Discuss with Fabio, an existing(old) dtb in mainline has to work in future
kernels,
without the need of being updated, so to add internal pll support for 6qp rgmii
gtx,
and not to break 6qp old dtb, add new property is one solution.
