[PATCH v1 05/17] clk: tegra30: Support custom CCLK implementation

[Dmitry Osipenko]

We're going to switch to the generic cpufreq-dt driver on Tegra30 and
thus CCLK intermediate re-parenting will be performed by the clock driver.
There is now special CCLK implementation that supports all CCLK quirks,
this patch makes Tegra30 SoCs to use that implementation.

Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
 drivers/clk/tegra/clk-tegra30.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 95b0e4a16dd5..ad545803af42 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params 
__ro_after_init = {
        .freq_table = pll_x_freq_table,
        .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
                 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
+       .pre_rate_change = tegra_cclk_pre_pllx_rate_change,
+       .post_rate_change = tegra_cclk_post_pllx_rate_change,
 };
 
 static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
@@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void)
        clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
 
        /* CCLKG */
-       clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
+       clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
                                  ARRAY_SIZE(cclk_g_parents),
                                  CLK_SET_RATE_PARENT,
                                  clk_base + CCLKG_BURST_POLICY,
-                                 0, 4, 0, 0, NULL);
+                                 0, NULL);
        clks[TEGRA30_CLK_CCLK_G] = clk;
 
        /*
-- 
2.23.0