Utilize common Tegra20 CPU OPP table. CPU voltage scaling is available now
on TrimSlice.

Signed-off-by: Dmitry Osipenko <dig...@gmail.com>
---
 arch/arm/boot/dts/tegra20-trimslice.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts 
b/arch/arm/boot/dts/tegra20-trimslice.dts
index 3e5ac096d85e..8debd3d3c20d 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -3,6 +3,7 @@
 
 #include <dt-bindings/input/input.h>
 #include "tegra20.dtsi"
+#include "tegra20-cpu-opp.dtsi"
 
 / {
        model = "Compulab TrimSlice board";
@@ -471,4 +472,14 @@
                         <&tegra_car TEGRA20_CLK_CDEV1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
+
+       cpus {
+               cpu0: cpu@0 {
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+
+               cpu@1 {
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+       };
 };
-- 
2.23.0

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