Add device-tree nodes for i2c0 to i2c2, and also add relevant pinctrl
nodes.

Suggested-by: Icenowy Zheng <icen...@aosc.io>
Signed-off-by: Bhushan Shah <bs...@kde.org>
---
Changes in v3:
  - fix compatible for the i2c
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 +++++++++++++++++++-
 1 file changed, 59 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index db71807255ef..5dc174715311 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -332,6 +332,21 @@
                                function = "hdmi";
                        };
 
+                       i2c0_pins: i2c0-pins {
+                               pins = "PD25", "PD26";
+                               function = "i2c0";
+                       };
+
+                       i2c1_pins: i2c1-pins {
+                               pins = "PH5", "PH6";
+                               function = "i2c1";
+                       };
+
+                       i2c2_pins: i2c2-pins {
+                               pins = "PD23", "PD24";
+                               function = "i2c2";
+                       };
+
                        mmc0_pins: mmc0-pins {
                                pins = "PF0", "PF1", "PF2", "PF3",
                                       "PF4", "PF5";
@@ -467,6 +482,48 @@
                        status = "disabled";
                };
 
+               i2c0: i2c@5002000 {
+                       compatible = "allwinner,sun50i-h6-i2c",
+                                    "allwinner,sun6i-a31-i2c";
+                       reg = <0x05002000 0x400>;
+                       interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2C0>;
+                       resets = <&ccu RST_BUS_I2C0>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c1: i2c@5002400 {
+                       compatible = "allwinner,sun50i-h6-i2c",
+                                    "allwinner,sun6i-a31-i2c";
+                       reg = <0x05002400 0x400>;
+                       interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2C1>;
+                       resets = <&ccu RST_BUS_I2C1>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c1_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               i2c2: i2c@5002800 {
+                       compatible = "allwinner,sun50i-h6-i2c",
+                                    "allwinner,sun6i-a31-i2c";
+                       reg = <0x05002800 0x400>;
+                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_I2C2>;
+                       resets = <&ccu RST_BUS_I2C2>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c2_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
                emac: ethernet@5020000 {
                        compatible = "allwinner,sun50i-h6-emac",
                                     "allwinner,sun50i-a64-emac";
@@ -798,7 +855,8 @@
                };
 
                r_i2c: i2c@7081400 {
-                       compatible = "allwinner,sun6i-a31-i2c";
+                       compatible = "allwinner,sun50i-h6-i2c",
+                                    "allwinner,sun6i-a31-i2c";
                        reg = <0x07081400 0x400>;
                        interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&r_ccu CLK_R_APB2_I2C>;
-- 
2.17.1

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