On Fri, Jun 7, 2019 at 3:10 PM Fenghua Yu <fenghua...@intel.com> wrote:
>
> C0.2 state in umwait and tpause instructions can be enabled or disabled
> on a processor through IA32_UMWAIT_CONTROL MSR register.
>
> +static u32 get_umwait_control_c02(void)
> +{
> + return umwait_control_cached & MSR_IA32_UMWAIT_CONTROL_C02;
> +}
> +
> +static u32 get_umwait_control_max_time(void)
> +{
> + return umwait_control_cached & MSR_IA32_UMWAIT_CONTROL_MAX_TIME;
> +}
> +
I'm not convinced that these helpers make the code any more readable.
