On Fri, Jun 07, 2019 at 03:00:35PM -0700, Fenghua Yu wrote: > C0.2 state in umwait and tpause instructions can be enabled or disabled > on a processor through IA32_UMWAIT_CONTROL MSR register. > > By default, C0.2 is enabled and the user wait instructions result in > lower power consumption with slower wakeup time. > > But in real time systems which require faster wakeup time although power > savings could be smaller, the administrator needs to disable C0.2 and all > C0.2 requests from user applications revert to C0.1. > > A sysfs interface "/sys/devices/system/cpu/umwait_control/enable_c02" is > created to allow the administrator to control C0.2 state during run time.
We already have an interface for applications to convey their latency requirements (pm-qos). We do not need another magic sys variable.
