> - A driver that blindly shoe-horns some value for the cache-line size must
> be fixed. Basically, it should not change the value if it is not zero and,
> at least, warn user if it has changed the value because it was zero.
> 
> What are the strong reasons that let some POST softwares not fill properly
> the cache line size of PCI devices ?

In part because it is not required to, and on x86 because there may be no
PCI configuration before the OS loader completes

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to [EMAIL PROTECTED]
Please read the FAQ at http://www.tux.org/lkml/

Reply via email to