Hi,
I noticed a lot of drivers are setting the PCI_CACHE_LINE_SIZE
themselves, some to L1_CACHE_BYTES/sizeof(u32), others
to arbitrary values (4, 8, 16).
Then I spotted that we have a routine in the PCI subsystem
(pdev_enable_device) that sets all these to L1_CACHE_BYTES/sizeof(u32)
Further digging revealed that this routine was not getting called.
On my Athlon box, I've noticed some devices are getting their
default values set to 8 (where (I think) it should be 16 ?)
Questions:
1. Is there reason for the drivers to be setting this themselves
to hardcoded values ?
2. Why is pdev_device_enable no longer used ?
regards,
Davej.
--
| Dave Jones <[EMAIL PROTECTED]> http://www.suse.de/~davej
| SuSE Labs
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