Quoting Paul Cercueil (2018-06-27 05:14:59) > The UDC clock of the JZ4740 SoC can be gated, but the data structure > representing it was missing the CGU_CLK_GATE flag to make it work. > > Signed-off-by: Paul Cercueil <p...@crapouillou.net> > ---
Applied to clk-next
