On 30/08/17 15:51, Vijay Viswanath wrote:
> From: Subhash Jadavani <subha...@codeaurora.org>
>
> SDCC controller reset (SW_RST) during probe may trigger power irq if
> previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we
> enable the power irq interrupt in GIC (by registering the interrupt
> handler), we need to ensure that any pending power irq interrupt status
> is acknowledged otherwise power irq interrupt handler would be fired
> prematurely.
>
> Signed-off-by: Subhash Jadavani <subha...@codeaurora.org>
> Signed-off-by: Vijay Viswanath <vvisw...@codeaurora.org>
Acked-by: Adrian Hunter <adrian.hun...@intel.com>
> ---
> drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 9d601dc..d636251 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -1250,6 +1250,21 @@ static int sdhci_msm_probe(struct platform_device
> *pdev)
> CORE_VENDOR_SPEC_CAPABILITIES0);
> }
>
> + /*
> + * Power on reset state may trigger power irq if previous status of
> + * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
> + * interrupt in GIC, any pending power irq interrupt should be
> + * acknowledged. Otherwise power irq interrupt handler would be
> + * fired prematurely.
> + */
> + sdhci_msm_voltage_switch(host);
> +
> + /*
> + * Ensure that above writes are propogated before interrupt enablement
> + * in GIC.
> + */
> + mb();
> +
> /* Setup IRQ for handling power/voltage tasks with PMIC */
> msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
> if (msm_host->pwr_irq < 0) {
> @@ -1259,6 +1274,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)
> goto clk_disable;
> }
>
> + /* Enable pwr irq interrupts */
> + writel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);
> +
> ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
> sdhci_msm_pwr_irq, IRQF_ONESHOT,
> dev_name(&pdev->dev), host);
>
