"Langsdorf, Mark" <[EMAIL PROTECTED]> writes: > > > If we really care about using the LAPIC timer on systems with deeper > > > than C1 support, the only alternative seems to be to test > > > if it actually works or not at boot and run-time. > > > Otherwise, we wait for future hardware with guaranteed > > > not to break under any (BIOS) conditions ships, and check for that. > > > > > > Based on what I read of the HP nx6325 where the LAPIC timer > > > is breaking C1, AMD is in the same boat. > > > > The nx6325 (Turion 64 X2) exports only C1. > > I'm not sure how the conclusion was drawn that it has > > a broken lapic timer as reflected in the "nolapic_timer" patch: > > If both cores goes into C1 at the same time, the chipset > can move the processor into a C3 like state called C1e.
... and that seems to break the local APIC timer. > AMD can craft a patch to sort this out as soon as we have > an idea what the framework is going to look like. Just a snippet to detect it would be great. Then the dmi scan could be removed and replaced with that. This would be a 2.6.21 candidate imho over the DMI hack. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
