On Mon, Jun 6, 2016 at 1:20 PM, Linda Knippers <linda.knipp...@hpe.com> wrote: [..] >> A solution to the posted-write-queue flushing needs to be available >> and a platform can choose to use flush hints or ADR. If the NFIT >> defines an NVDIMM device without hints we assume the platform must >> have ADR. If the platform NFIT neglects to define an NVDIMM to >> physical address range mapping, we warn about a potentially broken >> BIOS. Hopefully we can make this clearer in future versions of the >> spec. > > You lost me on those last 2 sentences. An NVDIMM doesn't have to have > an SPA range, but that seems to be unrelated to pcommit or flushes.
Ok, now you've lost me... We need a SPA range to be able to do I/O whether that SPA range is direct access to media or a block-window aperture. If an NFIT inculdes a "System Physical Address (SPA) Range Structure", but neglects to include a corresponding "NVDIMM Region Mapping Structure" then the kernel has no idea what actual dimm device(s) back that memory region. Without a memory device mapping it is undefined whether I/O to a SPA range requires flushing or not. This patch set silences the warning about "not being able to guarantee persistence" when the BIOS provides a "NVDIMM Region Mapping Structure". When that structure is present the kernel uses flush hints when provided, but ADR otherwise. See the implementation of nvdimm_flush() in patch 4.
