zhanchangbao-sanechips commented on PR #2639: URL: https://github.com/apache/orc/pull/2639#issuecomment-4716324936
> > Thanks for your interest in working on this! Before proceeding, I have some general questions: > > > > * Does it support a wide range of RISC-V family or just specific chips? > > * Is it possible to set up a CI workflow for this? Not sure if Github action already have this. > > * How do we want to maintain this in the future? > > > > cc @dongjoon-hyun @ffacs > > Thanks for your questions. > > > * It targets standard RISC-V Vector Extension 1.0 (RVV 1.0), not a specific chip, so it works across any RVV-compliant core regardless of vector register width. I've tested on two different platforms: SG2044 and K1. The detection logic behaves consistently across both. It's not tied to any specific chip. > > * GitHub Actions doesn't have native RISC-V runners yet. However, we can run tests under QEMU user-mode emulation (e.g., using qemu-riscv64-static). I can help set up a basic CI workflow that cross-compiles ORC for RISC-V and runs the test suite in emulation. It's slower than native but works on standard GitHub-hosted runners. > > * The code in this PR is intentionally minimal—just build flags and CPU detection. I plan to follow up with actual RVV optimizations in later PRs.Additionally, my company is currently investing in RISC-V porting and optimization work internally. So I intend to maintain this. This PR is part of a longer-term effort—we have ongoing plans to add RVV-accelerated bit unpacking and other SIMD optimizations. So this isn't a one-off contribution; there will be continued engineering resources behind it. > > Thanks for your interest in working on this! Before proceeding, I have some general questions: > > > > * Does it support a wide range of RISC-V family or just specific chips? > > * Is it possible to set up a CI workflow for this? Not sure if Github action already have this. > > * How do we want to maintain this in the future? > > > > cc @dongjoon-hyun @ffacs > > Thanks for your questions. > > > * It targets standard RISC-V Vector Extension 1.0 (RVV 1.0), not a specific chip, so it works across any RVV-compliant core regardless of vector register width. I've tested on two different platforms: SG2044 and K1. The detection logic behaves consistently across both. It's not tied to any specific chip. > > * GitHub Actions doesn't have native RISC-V runners yet. However, we can run tests under QEMU user-mode emulation (e.g., using qemu-riscv64-static). I can help set up a basic CI workflow that cross-compiles ORC for RISC-V and runs the test suite in emulation. It's slower than native but works on standard GitHub-hosted runners. > > * The code in this PR is intentionally minimal—just build flags and CPU detection. I plan to follow up with actual RVV optimizations in later PRs.Additionally, my company is currently investing in RISC-V porting and optimization work internally. So I intend to maintain this. This PR is part of a longer-term effort—we have ongoing plans to add RVV-accelerated bit unpacking and other SIMD optimizations. So this isn't a one-off contribution; there will be continued engineering resources behind it. I add a RISC-V CI workflow：this.https://github.com/apache/orc/pull/2644 -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
