zhanchangbao-sanechips opened a new pull request, #2639: URL: https://github.com/apache/orc/pull/2639
### What changes were proposed in this pull request? add the minimum to get RISC-V support in the build system and CPU detection. This is needed before can start add RVV-optimization. ### changes: - Added `BUILD_ENABLE_RVV` CMake option (off by default) - Added rv64gcv toolchain detection in `ConfigSimdLevel.cmake` - `ORC_USER_SIMD_LEVEL` now accepts RVV or NONE If RVV isn't available, it just falls back to scalar code. ### Why are the changes needed? ORC doesn't know anything about RISC-V. This is just the groundwork so follow-up patches can actually use RVV. (https://issues.apache.org/jira/browse/ORC-1971) ### How was this patch tested? - Tested on a Sophgo SG2044 board with GCC 14.2.0 - Built with `-DBUILD_ENABLE_RVV=ON`, config passed - Setting `ORC_USER_SIMD_LEVEL=NONE` properly masks out RVV -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
