On 03/17/2015 02:40 AM, Imre Deak wrote:
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++----
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 2 files changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9ca84a2..3606366 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -102,6 +102,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> static void intel_begin_crtc_commit(struct drm_crtc *crtc);
> static void intel_finish_crtc_commit(struct drm_crtc *crtc);
> +static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors);
>
> static struct intel_encoder *intel_find_encoder(struct intel_connector
> *connector, int pipe)
> {
> @@ -399,6 +400,18 @@ static const intel_limit_t intel_limits_chv = {
> .p2 = { .p2_slow = 1, .p2_fast = 14 },
> };
>
> +static const intel_limit_t intel_limits_bxt = {
> + /* FIXME: find real dot limits */
> + .dot = { .min = 0, .max = INT_MAX },
> + .vco = { .min = 4800000, .max = 6480000 },
> + .n = { .min = 1, .max = 1 },
> + .m1 = { .min = 2, .max = 2 },
> + /* FIXME: find real m2 limits */
> + .m2 = { .min = 2 << 22, .max = 255 << 22 },
> + .p1 = { .min = 2, .max = 4 },
> + .p2 = { .p2_slow = 1, .p2_fast = 20 },
> +};
> +
> static void vlv_clock(int refclk, intel_clock_t *clock)
> {
> clock->m = clock->m1 * clock->m2;
> @@ -492,7 +505,9 @@ static const intel_limit_t *intel_limit(struct intel_crtc
> *crtc, int refclk)
> struct drm_device *dev = crtc->base.dev;
> const intel_limit_t *limit;
>
> - if (HAS_PCH_SPLIT(dev))
> + if (IS_BROXTON(dev))
> + limit = &intel_limits_bxt;
> + else if (HAS_PCH_SPLIT(dev))
> limit = intel_ironlake_limit(crtc, refclk);
> else if (IS_G4X(dev)) {
> limit = intel_g4x_limit(crtc);
> @@ -577,11 +592,11 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
> if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
> INTELPllInvalid("m1 out of range\n");
>
> - if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
> + if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
> if (clock->m1 <= clock->m2)
> INTELPllInvalid("m1 <= m2\n");
>
> - if (!IS_VALLEYVIEW(dev)) {
> + if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
> if (clock->p < limit->p.min || limit->p.max < clock->p)
> INTELPllInvalid("p out of range\n");
> if (clock->m < limit->m.min || limit->m.max < clock->m)
> @@ -924,6 +939,15 @@ chv_find_best_dpll(const intel_limit_t *limit, struct
> intel_crtc *crtc,
> return found;
> }
>
> +bool bxt_find_best_dpll(struct intel_crtc *crtc, int target_clock,
> + intel_clock_t *best_clock)
> +{
> + int refclk = i9xx_get_refclk(crtc, 0);
> +
> + return chv_find_best_dpll(intel_limit(crtc, refclk), crtc, target_clock,
> + refclk, NULL, best_clock);
> +}
> +
> bool intel_crtc_active(struct drm_crtc *crtc)
> {
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> @@ -5913,7 +5937,7 @@ static int i9xx_get_refclk(struct intel_crtc *crtc, int
> num_connectors)
> struct drm_i915_private *dev_priv = dev->dev_private;
> int refclk;
>
> - if (IS_VALLEYVIEW(dev)) {
> + if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
> refclk = 100000;
> } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
> intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 262314b..56a5cc9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1033,6 +1033,8 @@ int intel_dotclock_calculate(int link_freq, const
> struct intel_link_m_n *m_n);
> void
> ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
> int dotclock);
> +bool bxt_find_best_dpll(struct intel_crtc *crtc, int target_clock,
> + intel_clock_t *best_clock);
> bool intel_crtc_active(struct drm_crtc *crtc);
> void hsw_enable_ips(struct intel_crtc *crtc);
> void hsw_disable_ips(struct intel_crtc *crtc);
>
Do we have a JIRA on getting the final pixel clock and M2 params? If
not, can you create one so we don't forget to add the real limits?
Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
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