From: Ville Syrjälä <[email protected]> We'll need to check for the "does the platform do 2 pixels per clock?" thing in a few places. Add a feature macro for it.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/display/intel_display_device.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 1d7ff2cbaebb..12bb6c414683 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2910,7 +2910,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) /* pixels per CDCLK */ int intel_cdclk_ppc(struct intel_display *display, bool double_wide) { - return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1; + return HAS_2PPC(display) || double_wide ? 2 : 1; } /* max pixel rate as % of CDCLK (not accounting for PPC) */ diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 9aeba329b9bd..7121e7cd9512 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -146,6 +146,7 @@ struct intel_display_platforms { func(supports_tv); #define HAS_128B_Y_TILING(__display) (!(__display)->platform.i915g && !(__display)->platform.i915gm) +#define HAS_2PPC(__display) (DISPLAY_VER(__display) >= 10) #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) -- 2.54.0
